RV_DM Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: 098010d125

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	3.090s	797.413us	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.990s	495.205us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.420s	631.791us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	29.910s	38.410ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	1.780s	1.298ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	8.480s	2.591ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	16.990s	5.960ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	3.721m	86.526ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	5.081m	222.695ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.260s	196.373us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.290s	245.070us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.520s	527.538us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.500s	324.667us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.170s	219.106us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.100s	489.859us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.060s	156.243us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	3.780s	1.155ms	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.260s	196.373us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.000s	214.298us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.190s	440.463us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.520s	527.538us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.200s	143.968us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.620s	144.292us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.540s	136.755us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.332m	80.725ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.267m	8.645ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	4.160s	78.991us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.267m	8.645ms	5	5	100.00
		rv_dm_csr_rw	2.540s	136.755us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.940s	102.162us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.820s	73.920us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	3.090s	797.413us	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.710s	817.721us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.060s	145.098us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.580s	626.624us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	3.230s	1.956ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	25.670s	8.959ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	32.850s	12.267ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	38.130s	13.843ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	43.310s	14.871ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.370s	261.468us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	2.250s	998.444us	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.340s	396.341us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.380s	307.097us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	7.010s	6.795ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	2.210m	5.374ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.050s	385.373us	1	1	100.00
V2	stress_all	rv_dm_stress_all	29.520s	9.879ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.130s	159.873us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	8.240s	2.885ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	8.240s	2.885ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.267m	8.645ms	5	5	100.00
		rv_dm_csr_hw_reset	2.620s	144.292us	5	5	100.00
		rv_dm_csr_rw	2.540s	136.755us	20	20	100.00
		rv_dm_same_csr_outstanding	9.250s	2.254ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.267m	8.645ms	5	5	100.00
		rv_dm_csr_hw_reset	2.620s	144.292us	5	5	100.00
		rv_dm_csr_rw	2.540s	136.755us	20	20	100.00
		rv_dm_same_csr_outstanding	9.250s	2.254ms	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	4.550s	1.285ms	5	5	100.00
		rv_dm_tl_intg_err	31.390s	5.222ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	31.390s	5.222ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	2.250s	998.444us	2	2	100.00
		rv_dm_debug_disabled	1.010s	110.003us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	2.250s	998.444us	2	2	100.00
		rv_dm_debug_disabled	1.010s	110.003us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	3.090s	797.413us	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	1.610s	342.386us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.050s	133.255us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.050s	133.255us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	1.610s	342.386us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.000m	3.771ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			482	482	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.14	96.32	87.27	92.10	93.59	90.44	98.74	58.53

Past Results

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