RV_DM Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: 584c3d46af

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	3.500s	1.619ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	3.800s	1.071ms	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.540s	649.722us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	1.805m	43.538ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	5.210s	1.812ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	27.790s	10.321ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	12.220s	11.382ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.436m	61.757ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	4.194m	90.487ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	4.130s	1.279ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.390s	283.374us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.880s	801.371us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.190s	592.691us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	0.990s	380.597us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.060s	912.080us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.840s	238.627us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.260s	1.063ms	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	4.130s	1.279ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.480s	595.115us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.850s	901.768us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.880s	801.371us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.890s	161.537us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.550s	534.488us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.430s	199.228us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.344m	23.534ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.236m	3.430ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	4.220s	210.435us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.236m	3.430ms	5	5	100.00
		rv_dm_csr_rw	2.430s	199.228us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.790s	43.925us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.860s	78.211us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	3.500s	1.619ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.330s	873.798us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.940s	450.983us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.380s	285.340us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.840s	939.728us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	29.680s	9.931ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	23.850s	8.991ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	35.060s	13.663ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	1.330m	52.819ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.510s	302.209us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	3.430s	3.493ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	0.990s	109.629us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.090s	189.309us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	4.500s	4.011ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.336m	8.486ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.860s	71.198us	1	1	100.00
V2	stress_all	rv_dm_stress_all	22.420s	7.634ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.090s	166.746us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	5.580s	947.556us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	5.580s	947.556us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.236m	3.430ms	5	5	100.00
		rv_dm_csr_hw_reset	2.550s	534.488us	5	5	100.00
		rv_dm_csr_rw	2.430s	199.228us	20	20	100.00
		rv_dm_same_csr_outstanding	7.850s	2.418ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.236m	3.430ms	5	5	100.00
		rv_dm_csr_hw_reset	2.550s	534.488us	5	5	100.00
		rv_dm_csr_rw	2.430s	199.228us	20	20	100.00
		rv_dm_same_csr_outstanding	7.850s	2.418ms	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	3.200s	2.920ms	5	5	100.00
		rv_dm_tl_intg_err	24.640s	7.648ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	24.640s	7.648ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	3.430s	3.493ms	2	2	100.00
		rv_dm_debug_disabled	0.850s	56.716us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	3.430s	3.493ms	2	2	100.00
		rv_dm_debug_disabled	0.850s	56.716us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	3.500s	1.619ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	2.290s	595.341us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.850s	105.335us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.850s	105.335us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	2.290s	595.341us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.661m	4.439ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			482	482	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.76	96.32	87.27	92.10	91.03	90.44	98.74	58.45

Past Results

• Latest
• lint
• 2024.08.14_08.40.56
• 2024.08.13_08.07.35
• 2024.08.12_08.37.00
• 2024.08.11_08.22.55
• 2024.08.10_08.28.01
• 2024.08.09_07.58.31