RV_DM Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	5.790s	3.441ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	2.340s	567.472us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.640s	781.760us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	46.230s	18.290ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	3.290s	923.834us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	11.160s	7.181ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	39.380s	13.226ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.264m	83.881ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	5.544m	238.657ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.290s	465.602us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.150s	582.771us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.950s	813.784us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.530s	588.862us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	0.920s	95.637us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.670s	669.275us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.920s	267.225us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	4.110s	1.312ms	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.290s	465.602us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.530s	585.812us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.470s	269.367us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.950s	813.784us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.050s	92.225us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.730s	253.899us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.540s	382.442us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.235m	6.422ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.375m	22.026ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	3.870s	246.762us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.375m	22.026ms	5	5	100.00
		rv_dm_csr_rw	2.540s	382.442us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.790s	64.958us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.770s	169.330us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	5.790s	3.441ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.050s	412.164us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.150s	312.955us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.370s	535.416us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.010s	521.906us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	14.300s	7.817ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	40.410s	14.232ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	19.840s	9.606ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	3.455m	208.974ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.600s	649.937us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	5.100s	1.808ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.510s	350.333us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.440s	292.502us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	6.800s	3.606ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.688m	4.696ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.840s	134.206us	1	1	100.00
V2	stress_all	rv_dm_stress_all	28.160s	10.173ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.010s	113.373us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	5.490s	305.599us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	5.490s	305.599us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.375m	22.026ms	5	5	100.00
		rv_dm_csr_hw_reset	2.730s	253.899us	5	5	100.00
		rv_dm_csr_rw	2.540s	382.442us	20	20	100.00
		rv_dm_same_csr_outstanding	8.590s	724.167us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.375m	22.026ms	5	5	100.00
		rv_dm_csr_hw_reset	2.730s	253.899us	5	5	100.00
		rv_dm_csr_rw	2.540s	382.442us	20	20	100.00
		rv_dm_same_csr_outstanding	8.590s	724.167us	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	4.310s	2.736ms	5	5	100.00
		rv_dm_tl_intg_err	34.900s	6.362ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	34.900s	6.362ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	5.100s	1.808ms	2	2	100.00
		rv_dm_debug_disabled	0.920s	42.896us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	5.100s	1.808ms	2	2	100.00
		rv_dm_debug_disabled	0.920s	42.896us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	5.790s	3.441ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	2.080s	512.729us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.000s	284.122us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.000s	284.122us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	2.080s	512.729us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.793m	10.623ms	10	10	100.00
V3		TOTAL			10	10	100.00
	Unmapped tests	rv_dm_scanmode	0.680s	19.534us	1	1	100.00
		TOTAL			483	483	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.09	96.32	89.53	92.10	93.33	90.44	98.74	56.17

Past Results

• Latest
• lint
• 2024.08.15_05.36.46
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• 2024.08.13_08.07.35
• 2024.08.12_08.37.00
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