RV_DM Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	4.660s	2.858ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.860s	779.302us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	1.960s	526.652us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	27.440s	16.971ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	5.570s	2.014ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	37.160s	19.694ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	21.390s	7.559ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.586m	72.382ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	4.609m	201.580ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.990s	427.635us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	2.220s	532.103us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.030s	250.818us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.320s	219.023us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.180s	454.730us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.100s	1.492ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.820s	430.984us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.460s	704.042us	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.990s	427.635us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.870s	166.333us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	3.380s	1.108ms	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.030s	250.818us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.950s	144.283us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.120s	274.289us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.580s	189.997us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.107m	20.373ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.416m	18.305ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	4.510s	151.581us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.416m	18.305ms	5	5	100.00
		rv_dm_csr_rw	2.580s	189.997us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.940s	104.572us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.780s	117.115us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	4.660s	2.858ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.490s	304.836us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	2.500s	660.099us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.380s	473.531us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.160s	872.855us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	10.170s	6.262ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	29.160s	9.004ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	37.170s	12.954ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	4.436m	93.385ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	0.850s	177.306us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	3.480s	3.948ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.460s	796.982us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	0.780s	80.088us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	23.590s	8.785ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.340m	12.981ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.670s	373.799us	1	1	100.00
V2	stress_all	rv_dm_stress_all	25.240s	16.996ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.120s	154.041us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	6.010s	923.308us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	6.010s	923.308us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.416m	18.305ms	5	5	100.00
		rv_dm_csr_hw_reset	2.120s	274.289us	5	5	100.00
		rv_dm_csr_rw	2.580s	189.997us	20	20	100.00
		rv_dm_same_csr_outstanding	8.650s	760.700us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.416m	18.305ms	5	5	100.00
		rv_dm_csr_hw_reset	2.120s	274.289us	5	5	100.00
		rv_dm_csr_rw	2.580s	189.997us	20	20	100.00
		rv_dm_same_csr_outstanding	8.650s	760.700us	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	8.750s	2.814ms	5	5	100.00
		rv_dm_tl_intg_err	30.110s	5.103ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	30.110s	5.103ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	3.480s	3.948ms	2	2	100.00
		rv_dm_debug_disabled	0.970s	63.099us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	3.480s	3.948ms	2	2	100.00
		rv_dm_debug_disabled	0.970s	63.099us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	4.660s	2.858ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	1.610s	698.095us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.160s	148.090us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.160s	148.090us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	1.610s	698.095us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	59.200s	2.406ms	10	10	100.00
V3		TOTAL			10	10	100.00
	Unmapped tests	rv_dm_scanmode	0.690s	23.889us	1	1	100.00
		TOTAL			483	483	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.46	96.32	89.96	92.10	93.33	90.44	98.63	58.45

Past Results

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• 2024.08.16_08.41.16
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• 2024.08.13_08.07.35
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