RV_DM Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 5.760s 3.567ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.020s 386.356us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.400s 756.005us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 1.076m 43.481ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 3.350s 2.539ms 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 16.190s 5.398ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 16.900s 5.795ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.552m 34.249ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 3.984m 85.660ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.910s 1.388ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.170s 361.974us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 0.910s 316.921us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.680s 751.345us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.090s 581.590us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.150s 656.931us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.130s 250.889us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.510s 1.317ms 8 8 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.910s 1.388ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.850s 207.896us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.550s 602.665us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 0.910s 316.921us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.910s 154.484us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.530s 505.559us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.640s 189.671us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.325m 25.792ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.108m 1.181ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 4.020s 207.562us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.108m 1.181ms 5 5 100.00
rv_dm_csr_rw 2.640s 189.671us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.770s 169.558us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.880s 160.443us 5 5 100.00
V1 TOTAL 180 180 100.00
V2 idcode rv_dm_smoke 5.760s 3.567ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.310s 700.499us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.190s 859.382us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 0.860s 146.444us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 4.400s 2.507ms 2 2 100.00
V2 sba rv_dm_sba_tl_access 34.990s 15.996ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 35.170s 12.720ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 27.460s 11.594ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 5.256m 125.303ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.030s 692.040us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 8.860s 4.986ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.490s 293.041us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 0.970s 145.488us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 7.290s 5.915ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.475m 4.513ms 10 10 100.00
V2 hartsel_warl rv_dm_hartsel_warl 0.820s 70.378us 1 1 100.00
V2 stress_all rv_dm_stress_all 28.300s 10.223ms 50 50 100.00
V2 alert_test rv_dm_alert_test 1.070s 146.413us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 5.510s 313.599us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 5.510s 313.599us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.108m 1.181ms 5 5 100.00
rv_dm_csr_hw_reset 2.530s 505.559us 5 5 100.00
rv_dm_csr_rw 2.640s 189.671us 20 20 100.00
rv_dm_same_csr_outstanding 7.780s 508.483us 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.108m 1.181ms 5 5 100.00
rv_dm_csr_hw_reset 2.530s 505.559us 5 5 100.00
rv_dm_csr_rw 2.640s 189.671us 20 20 100.00
rv_dm_same_csr_outstanding 7.780s 508.483us 20 20 100.00
V2 TOTAL 251 251 100.00
V2S tl_intg_err rv_dm_sec_cm 3.550s 986.028us 5 5 100.00
rv_dm_tl_intg_err 21.110s 3.623ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 21.110s 3.623ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 8.860s 4.986ms 2 2 100.00
rv_dm_debug_disabled 0.910s 56.153us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 8.860s 4.986ms 2 2 100.00
rv_dm_debug_disabled 0.910s 56.153us 2 2 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 5.760s 3.567ms 2 2 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.950s 441.250us 10 10 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.620s 329.019us 4 4 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.620s 329.019us 4 4 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.950s 441.250us 10 10 100.00
V2S TOTAL 41 41 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.503m 11.584ms 10 10 100.00
V3 TOTAL 10 10 100.00
Unmapped tests rv_dm_scanmode 0.690s 15.339us 1 1 100.00
TOTAL 483 483 100.00

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 1 100.00
V1 27 27 27 100.00
V2 19 19 19 100.00
V2S 5 5 5 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
88.53 96.32 89.25 92.10 94.67 90.27 98.63 58.45

Past Results