RV_DM Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 3.400s 1.917ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.950s 985.341us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 3.730s 1.138ms 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 22.290s 11.785ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.000s 485.296us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 13.100s 17.203ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 18.270s 13.356ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 2.493m 53.178ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 5.927m 139.936ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.180s 273.469us 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 2.240s 673.687us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 0.920s 149.713us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 0.920s 189.849us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.940s 139.337us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 0.960s 461.588us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.020s 268.512us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.290s 555.499us 8 8 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.180s 273.469us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.820s 157.565us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.290s 1.209ms 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 0.920s 149.713us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.830s 124.469us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.480s 664.967us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.520s 163.707us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 56.210s 1.845ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.132m 1.217ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 4.160s 103.152us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.132m 1.217ms 5 5 100.00
rv_dm_csr_rw 2.520s 163.707us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.860s 60.691us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.830s 60.195us 5 5 100.00
V1 TOTAL 180 180 100.00
V2 idcode rv_dm_smoke 3.400s 1.917ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.120s 595.715us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0.920s 234.978us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.200s 615.023us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.840s 415.958us 2 2 100.00
V2 sba rv_dm_sba_tl_access 12.860s 4.872ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 35.630s 13.393ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 24.100s 8.376ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.726m 93.379ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.920s 671.893us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 7.210s 2.790ms 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.060s 263.273us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.370s 259.019us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 4.060s 8.011ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 2.058m 9.347ms 10 10 100.00
V2 hartsel_warl rv_dm_hartsel_warl 0.780s 133.969us 1 1 100.00
V2 stress_all rv_dm_stress_all 18.990s 6.212ms 50 50 100.00
V2 alert_test rv_dm_alert_test 0.980s 116.039us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.930s 347.126us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.930s 347.126us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.132m 1.217ms 5 5 100.00
rv_dm_csr_hw_reset 2.480s 664.967us 5 5 100.00
rv_dm_csr_rw 2.520s 163.707us 20 20 100.00
rv_dm_same_csr_outstanding 8.310s 806.526us 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.132m 1.217ms 5 5 100.00
rv_dm_csr_hw_reset 2.480s 664.967us 5 5 100.00
rv_dm_csr_rw 2.520s 163.707us 20 20 100.00
rv_dm_same_csr_outstanding 8.310s 806.526us 20 20 100.00
V2 TOTAL 251 251 100.00
V2S tl_intg_err rv_dm_sec_cm 2.890s 1.382ms 5 5 100.00
rv_dm_tl_intg_err 26.960s 5.093ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 26.960s 5.093ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 7.210s 2.790ms 2 2 100.00
rv_dm_debug_disabled 0.970s 85.523us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 7.210s 2.790ms 2 2 100.00
rv_dm_debug_disabled 0.970s 85.523us 2 2 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 3.400s 1.917ms 2 2 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 2.610s 694.733us 10 10 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 0.930s 262.036us 4 4 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 0.930s 262.036us 4 4 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 2.610s 694.733us 10 10 100.00
V2S TOTAL 41 41 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.451m 15.308ms 10 10 100.00
V3 TOTAL 10 10 100.00
Unmapped tests rv_dm_scanmode 0.660s 34.777us 1 1 100.00
TOTAL 483 483 100.00

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 1 100.00
V1 27 27 27 100.00
V2 19 19 19 100.00
V2S 5 5 5 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
87.82 96.32 89.53 92.10 92.00 90.44 98.21 56.10

Past Results