RV_DM Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: e45ccd274a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	1.820s	1.048ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.770s	455.400us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.150s	693.918us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	1.263m	30.433ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.590s	1.261ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	51.050s	21.092ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	21.060s	14.930ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.021m	25.854ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	3.825m	83.495ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	3.930s	1.092ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.180s	197.868us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.120s	142.517us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.620s	711.374us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.510s	293.348us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.030s	747.916us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.900s	315.709us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.300s	585.567us	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	3.930s	1.092ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.230s	198.740us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	2.390s	1.173ms	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.120s	142.517us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.880s	203.812us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.680s	648.754us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.590s	204.027us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.142m	27.187ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.329m	8.908ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	3.990s	162.195us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.329m	8.908ms	5	5	100.00
		rv_dm_csr_rw	2.590s	204.027us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.920s	104.644us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.060s	179.113us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	1.820s	1.048ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.440s	413.221us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	2.490s	612.766us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.020s	196.489us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	3.380s	1.041ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	25.250s	9.188ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	33.330s	12.176ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	25.780s	17.875ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	1.623m	79.425ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.040s	133.248us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	3.190s	946.262us	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.440s	437.134us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.020s	123.851us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	7.620s	6.916ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	2.030m	38.757ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.760s	159.709us	1	1	100.00
V2	stress_all	rv_dm_stress_all	20.310s	7.111ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.010s	129.773us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	5.520s	818.066us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	5.520s	818.066us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.329m	8.908ms	5	5	100.00
		rv_dm_csr_hw_reset	2.680s	648.754us	5	5	100.00
		rv_dm_csr_rw	2.590s	204.027us	20	20	100.00
		rv_dm_same_csr_outstanding	8.320s	7.807ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.329m	8.908ms	5	5	100.00
		rv_dm_csr_hw_reset	2.680s	648.754us	5	5	100.00
		rv_dm_csr_rw	2.590s	204.027us	20	20	100.00
		rv_dm_same_csr_outstanding	8.320s	7.807ms	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	4.720s	1.251ms	5	5	100.00
		rv_dm_tl_intg_err	24.150s	3.285ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	24.150s	3.285ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	3.190s	946.262us	2	2	100.00
		rv_dm_debug_disabled	0.850s	95.757us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	3.190s	946.262us	2	2	100.00
		rv_dm_debug_disabled	0.850s	95.757us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	1.820s	1.048ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	2.350s	615.582us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.150s	271.592us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.150s	271.592us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	2.350s	615.582us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.832m	8.474ms	8	10	80.00
V3		TOTAL			8	10	80.00
	Unmapped tests	rv_dm_scanmode	0.680s	23.281us	1	1	100.00
		TOTAL			481	483	99.59

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.20	96.32	89.82	92.10	96.00	90.44	98.74	54.00

Failure Buckets

• UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:62) [rv_dm_mem_tl_access_resuming_vseq] Check failed dmi_status == UVM_IS_OK (* [*] vs * [*]) has 2 failures:
  • Test rv_dm_stress_all_with_rand_reset has 2 failures.

    • 6.rv_dm_stress_all_with_rand_reset.79446069261052402502256260444882598353431415579136095372778666870834356098915
      Line 332, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14046542090 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed dmi_status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 14046542090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 7.rv_dm_stress_all_with_rand_reset.15520131678975198094359721722217228417458934425613805001236349155558761741869
      Line 285, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1446838149 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed dmi_status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 1446838149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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