RV_DM Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: 34b8fc33e3

Branch: earlgrey_1_0_0_2024_08_20_RC0

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	4.070s	1.092ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.730s	1.128ms	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	4.140s	547.541us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	1.273m	28.250ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	3.200s	1.582ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	46.490s	13.787ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	46.320s	14.660ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.698m	35.954ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	4.249m	101.331ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	3.090s	463.458us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.650s	392.540us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.480s	390.069us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.210s	306.008us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	2.680s	516.523us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	3.930s	1.190ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.090s	133.894us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	4.260s	1.361ms	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	3.090s	463.458us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.260s	422.528us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.160s	207.509us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.480s	390.069us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.300s	37.260us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	3.340s	1.193ms	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	3.050s	164.695us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	50.460s	17.514ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.253m	3.651ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	5.290s	107.964us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.253m	3.651ms	5	5	100.00
		rv_dm_csr_rw	3.050s	164.695us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.990s	71.726us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.680s	118.111us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	4.070s	1.092ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	2.220s	743.479us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.380s	419.298us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.230s	172.944us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	4.310s	1.496ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	29.900s	17.685ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	29.360s	15.477ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	22.870s	6.268ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	5.269m	113.654ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	2.890s	674.264us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	6.420s	1.517ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.290s	219.888us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	2.250s	326.349us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	10.270s	8.984ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.934m	8.665ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.470s	268.114us	1	1	100.00
V2	stress_all	rv_dm_stress_all	19.440s	5.936ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.600s	127.796us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	8.240s	366.257us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	8.240s	366.257us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.253m	3.651ms	5	5	100.00
		rv_dm_csr_hw_reset	3.340s	1.193ms	5	5	100.00
		rv_dm_csr_rw	3.050s	164.695us	20	20	100.00
		rv_dm_same_csr_outstanding	9.250s	232.978us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.253m	3.651ms	5	5	100.00
		rv_dm_csr_hw_reset	3.340s	1.193ms	5	5	100.00
		rv_dm_csr_rw	3.050s	164.695us	20	20	100.00
		rv_dm_same_csr_outstanding	9.250s	232.978us	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	10.530s	2.735ms	5	5	100.00
		rv_dm_tl_intg_err	33.510s	5.114ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	33.510s	5.114ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	6.420s	1.517ms	2	2	100.00
		rv_dm_debug_disabled	1.290s	176.849us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	6.420s	1.517ms	2	2	100.00
		rv_dm_debug_disabled	1.290s	176.849us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	4.070s	1.092ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	3.190s	727.794us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	2.160s	244.050us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	2.160s	244.050us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	3.190s	727.794us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.150m	16.784ms	9	10	90.00
V3		TOTAL			9	10	90.00
	Unmapped tests	rv_dm_scanmode	0.860s	11.308us	1	1	100.00
		TOTAL			482	483	99.79

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.24	96.32	89.82	92.10	94.67	90.44	98.00	56.31

Failure Buckets

• UVM_ERROR (rv_dm_base_vseq.sv:391) [rv_dm_jtag_dtm_idle_hint_vseq] Check failed expected_dmistat == get_field_val(jtag_dtm_ral.dtmcs.dmistat, rdata) (* [*] vs * [*]) has 1 failures:
  • Test rv_dm_stress_all_with_rand_reset has 1 failures.

    • 5.rv_dm_stress_all_with_rand_reset.4829857774863241832629308856184594629123831815839655607464628146947933264578
      Line 152, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5642471248 ps: (rv_dm_base_vseq.sv:391) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_idle_hint_vseq] Check failed expected_dmistat == get_field_val(jtag_dtm_ral.dtmcs.dmistat, rdata) (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 5642471248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.08.20_08.00.53
• 2024.08.19_08.14.40
• 2024.08.18_08.42.00
• 2024.08.17_07.21.35
• 2024.08.16_08.41.16
• 2024.08.15_05.36.46