RV_DM Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	2.780s	2.090ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.040s	359.679us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	3.080s	1.046ms	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	33.740s	25.827ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	1.910s	582.112us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	22.990s	8.487ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	23.240s	15.157ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.766m	38.436ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	3.561m	87.558ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.350s	1.161ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	2.450s	783.857us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.540s	353.079us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.340s	330.454us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	2.390s	621.839us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	3.130s	1.043ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.740s	399.497us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.730s	763.087us	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.350s	1.161ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.820s	130.378us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.090s	166.367us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.540s	353.079us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.840s	77.177us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	1.950s	95.322us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.130s	164.793us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.132m	91.257ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.093m	15.780ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	3.740s	174.114us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.093m	15.780ms	5	5	100.00
		rv_dm_csr_rw	2.130s	164.793us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.940s	144.112us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.680s	148.714us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	2.780s	2.090ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	0.870s	588.322us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.280s	270.838us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	2.290s	638.403us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.110s	1.791ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	23.490s	8.208ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	22.720s	14.270ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	25.650s	9.442ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.841m	60.746ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.860s	546.666us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	3.190s	2.647ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.400s	317.826us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	0.740s	93.049us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	8.960s	11.416ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.287m	21.012ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.740s	51.322us	1	1	100.00
V2	stress_all	rv_dm_stress_all	20.070s	13.973ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	0.970s	155.126us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	5.190s	151.413us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	5.190s	151.413us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.093m	15.780ms	5	5	100.00
		rv_dm_csr_hw_reset	1.950s	95.322us	5	5	100.00
		rv_dm_csr_rw	2.130s	164.793us	20	20	100.00
		rv_dm_same_csr_outstanding	7.930s	3.685ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.093m	15.780ms	5	5	100.00
		rv_dm_csr_hw_reset	1.950s	95.322us	5	5	100.00
		rv_dm_csr_rw	2.130s	164.793us	20	20	100.00
		rv_dm_same_csr_outstanding	7.930s	3.685ms	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	4.180s	1.304ms	5	5	100.00
		rv_dm_tl_intg_err	26.590s	5.200ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	26.590s	5.200ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	3.190s	2.647ms	2	2	100.00
		rv_dm_debug_disabled	0.840s	168.649us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	3.190s	2.647ms	2	2	100.00
		rv_dm_debug_disabled	0.840s	168.649us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	2.780s	2.090ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	1.440s	273.704us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.830s	139.100us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.830s	139.100us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	1.440s	273.704us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.722m	5.415ms	10	10	100.00
V3		TOTAL			10	10	100.00
	Unmapped tests	rv_dm_scanmode	0.610s	30.119us	1	1	100.00
		TOTAL			483	483	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.13	96.32	90.10	92.10	94.67	90.78	98.74	61.18

Past Results

• Latest
• lint
• 2024.08.22_14.17.49
• 2024.08.20_08.00.53
• 2024.08.19_08.14.40
• 2024.08.18_08.42.00
• 2024.08.17_07.21.35
• 2024.08.16_08.41.16