RV_DM Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: e733a8ef8a

Branch: os_regression_2024_08_24

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 8.990s 1.331ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 5.180s 1.421ms 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.700s 350.627us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 1.240m 14.512ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 3.520s 529.185us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 1.100m 20.278ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 41.820s 7.269ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 6.448m 72.234ms 20 20 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.964m 50.316ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 2.650s 1.249ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 2.940s 310.894us 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.440s 290.543us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.950s 706.191us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 3.020s 372.992us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 3.140s 333.833us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.440s 95.857us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 8.220s 1.343ms 8 8 100.00
V1 progbuf_busy rv_dm_cmderr_busy 2.650s 1.249ms 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.320s 152.065us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 4.690s 665.295us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.440s 290.543us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 1.450s 42.471us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 4.020s 389.709us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 3.730s 294.903us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.054m 1.506ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.869m 10.316ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 5.390s 165.872us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.869m 10.316ms 5 5 100.00
rv_dm_csr_rw 3.730s 294.903us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 1.320s 71.866us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.350s 78.849us 5 5 100.00
V1 TOTAL 180 180 100.00
V2 idcode rv_dm_smoke 8.990s 1.331ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 5.490s 793.426us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.940s 302.396us 2 2 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 2.100s 594.204us 2 2 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 4.060s 795.395us 2 2 100.00
V2 sba rv_dm_sba_tl_access 48.990s 13.901ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 1.074m 11.054ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 50.270s 16.443ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.312m 28.515ms 20 20 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 3.400s 656.698us 2 2 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 4.140s 819.432us 2 2 100.00
V2 ndmreset_req rv_dm_ndmreset_req 2.020s 290.395us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.510s 83.451us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 21.390s 7.569ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 2.500m 12.218ms 10 10 100.00
V2 hartsel_warl rv_dm_hartsel_warl 1.550s 148.528us 1 1 100.00
V2 stress_all rv_dm_stress_all 47.970s 11.332ms 50 50 100.00
V2 alert_test rv_dm_alert_test 1.860s 154.564us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 9.040s 858.058us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 9.040s 858.058us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.869m 10.316ms 5 5 100.00
rv_dm_csr_hw_reset 4.020s 389.709us 5 5 100.00
rv_dm_csr_rw 3.730s 294.903us 20 20 100.00
rv_dm_same_csr_outstanding 12.620s 529.862us 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.869m 10.316ms 5 5 100.00
rv_dm_csr_hw_reset 4.020s 389.709us 5 5 100.00
rv_dm_csr_rw 3.730s 294.903us 20 20 100.00
rv_dm_same_csr_outstanding 12.620s 529.862us 20 20 100.00
V2 TOTAL 251 251 100.00
V2S tl_intg_err rv_dm_sec_cm 5.760s 1.272ms 5 5 100.00
rv_dm_tl_intg_err 36.100s 5.147ms 20 20 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 36.100s 5.147ms 20 20 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 4.140s 819.432us 2 2 100.00
rv_dm_debug_disabled 1.410s 44.026us 2 2 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 4.140s 819.432us 2 2 100.00
rv_dm_debug_disabled 1.410s 44.026us 2 2 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 8.990s 1.331ms 2 2 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 2.610s 330.505us 10 10 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.750s 335.914us 4 4 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.750s 335.914us 4 4 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 2.610s 330.505us 10 10 100.00
V2S TOTAL 41 41 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 2.102m 3.970ms 10 10 100.00
V3 TOTAL 10 10 100.00
Unmapped tests rv_dm_scanmode 0.960s 12.921us 1 1 100.00
TOTAL 483 483 100.00

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 1 100.00
V1 27 27 27 100.00
V2 19 19 19 100.00
V2S 5 5 5 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
88.96 96.32 89.67 92.10 94.67 90.27 98.53 61.18

Past Results