RV_DM Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	3.790s	705.976us	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.570s	343.225us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	3.070s	368.868us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	1.521m	26.875ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	5.130s	623.708us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	26.070s	17.496ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	27.430s	5.345ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.730m	53.287ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	3.091m	105.113ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	2.040s	176.068us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.530s	139.547us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.460s	372.182us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.360s	241.270us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.140s	146.504us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.830s	610.856us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.200s	230.482us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	5.250s	1.219ms	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	2.040s	176.068us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.150s	197.429us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.420s	207.686us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.460s	372.182us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.380s	93.028us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.530s	307.914us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	3.400s	144.886us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.475m	25.288ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.241m	6.737ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	5.320s	93.159us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.241m	6.737ms	5	5	100.00
		rv_dm_csr_rw	3.400s	144.886us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.420s	79.246us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.190s	175.943us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	3.790s	705.976us	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.420s	335.048us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.300s	111.960us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.370s	214.634us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.760s	2.168ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	37.420s	13.278ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	16.890s	10.935ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	20.670s	13.797ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	8.507m	187.003ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.450s	436.074us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	4.050s	2.139ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	2.380s	348.948us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.300s	348.593us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	6.110s	8.675ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.401m	41.366ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.840s	114.699us	1	1	100.00
V2	stress_all	rv_dm_stress_all	27.410s	10.871ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.560s	104.455us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	8.160s	714.747us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	8.160s	714.747us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.241m	6.737ms	5	5	100.00
		rv_dm_csr_hw_reset	2.530s	307.914us	5	5	100.00
		rv_dm_csr_rw	3.400s	144.886us	20	20	100.00
		rv_dm_same_csr_outstanding	12.610s	1.128ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.241m	6.737ms	5	5	100.00
		rv_dm_csr_hw_reset	2.530s	307.914us	5	5	100.00
		rv_dm_csr_rw	3.400s	144.886us	20	20	100.00
		rv_dm_same_csr_outstanding	12.610s	1.128ms	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	3.910s	479.639us	5	5	100.00
		rv_dm_tl_intg_err	26.640s	6.526ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	26.640s	6.526ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	4.050s	2.139ms	2	2	100.00
		rv_dm_debug_disabled	1.330s	111.404us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	4.050s	2.139ms	2	2	100.00
		rv_dm_debug_disabled	1.330s	111.404us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	3.790s	705.976us	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	3.760s	627.847us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.480s	250.177us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.480s	250.177us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	3.760s	627.847us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.477m	4.116ms	10	10	100.00
V3		TOTAL			10	10	100.00
	Unmapped tests	rv_dm_scanmode	0.980s	14.676us	1	1	100.00
		TOTAL			483	483	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.80	96.32	89.67	92.10	93.33	90.44	98.53	61.18

Past Results

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• 2024.08.26_02.20.16
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