RV_DM Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: a861deb3de

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	11.510s	2.200ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	2.670s	595.632us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	4.360s	693.690us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	33.400s	18.793ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	7.480s	1.093ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	24.170s	18.118ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	1.057m	15.347ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.435m	54.887ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	1.239m	43.016ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	2.310s	395.346us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	3.100s	791.266us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	5.320s	788.409us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.050s	662.528us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.160s	81.712us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	3.070s	3.079ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.480s	97.628us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	3.090s	914.259us	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	2.310s	395.346us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.790s	515.182us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	4.320s	467.636us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	5.320s	788.409us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.160s	91.139us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	3.930s	365.356us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	3.540s	351.233us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.240m	23.469ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.567m	4.522ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	5.240s	185.969us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.567m	4.522ms	5	5	100.00
		rv_dm_csr_rw	3.540s	351.233us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.540s	134.709us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.470s	112.563us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	11.510s	2.200ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	4.400s	629.179us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.510s	248.182us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	2.140s	398.696us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	3.200s	2.282ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	41.350s	10.697ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	51.880s	14.531ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	24.230s	9.004ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	3.572m	63.084ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	2.080s	185.728us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	13.300s	2.639ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.990s	700.024us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.340s	203.642us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	6.850s	4.134ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.575m	63.057ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.280s	67.294us	1	1	100.00
V2	stress_all	rv_dm_stress_all	46.550s	11.764ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.770s	125.760us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	7.580s	442.771us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	7.580s	442.771us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.567m	4.522ms	5	5	100.00
		rv_dm_csr_hw_reset	3.930s	365.356us	5	5	100.00
		rv_dm_csr_rw	3.540s	351.233us	20	20	100.00
		rv_dm_same_csr_outstanding	11.710s	572.245us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.567m	4.522ms	5	5	100.00
		rv_dm_csr_hw_reset	3.930s	365.356us	5	5	100.00
		rv_dm_csr_rw	3.540s	351.233us	20	20	100.00
		rv_dm_same_csr_outstanding	11.710s	572.245us	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	8.060s	2.355ms	5	5	100.00
		rv_dm_tl_intg_err	42.860s	4.255ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	42.860s	4.255ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	13.300s	2.639ms	2	2	100.00
		rv_dm_debug_disabled	1.300s	64.129us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	13.300s	2.639ms	2	2	100.00
		rv_dm_debug_disabled	1.300s	64.129us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	11.510s	2.200ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	2.500s	483.834us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.850s	287.309us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.850s	287.309us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	2.500s	483.834us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.947m	64.480ms	9	10	90.00
V3		TOTAL			9	10	90.00
	Unmapped tests	rv_dm_scanmode	1.030s	57.571us	1	1	100.00
		TOTAL			482	483	99.79

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.83	96.32	89.96	92.10	93.33	90.44	98.63	61.04

Failure Buckets

• UVM_ERROR (rv_dm_base_vseq.sv:391) [rv_dm_jtag_dtm_idle_hint_vseq] Check failed expected_dmistat == get_field_val(jtag_dtm_ral.dtmcs.dmistat, rdata) (* [*] vs * [*]) has 1 failures:
  • Test rv_dm_stress_all_with_rand_reset has 1 failures.

    • 2.rv_dm_stress_all_with_rand_reset.32918618460897613054025608147072478518032970291399924134961757415551487028664
      Line 96, in log /workspaces/repo/scratch/os_regression_2024_08_28/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 699826875 ps: (rv_dm_base_vseq.sv:391) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_idle_hint_vseq] Check failed expected_dmistat == get_field_val(jtag_dtm_ral.dtmcs.dmistat, rdata) (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 699826875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.08.28_06.58.46
• 2024.08.26_02.20.16
• 2024.08.24_20.16.10
• 2024.08.22_14.17.49
• 2024.08.20_08.00.53
• 2024.08.19_08.14.40