RV_DM Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	10.110s	2.461ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	3.390s	490.995us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.580s	486.435us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	18.390s	3.498ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	7.100s	1.355ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	19.340s	5.932ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	53.450s	14.088ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	3.502m	78.043ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	8.685m	140.694ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	4.940s	1.089ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.770s	188.657us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.960s	367.243us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.730s	366.149us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	4.380s	569.565us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.580s	775.088us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	2.600s	269.098us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	4.120s	1.265ms	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	4.940s	1.089ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.510s	158.242us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.470s	203.149us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.960s	367.243us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.740s	124.657us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	4.040s	345.277us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	3.730s	254.750us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.403m	55.933ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.465m	7.932ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	5.910s	147.565us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.465m	7.932ms	5	5	100.00
		rv_dm_csr_rw	3.730s	254.750us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.380s	131.116us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.340s	114.738us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	10.110s	2.461ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.340s	106.165us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	2.820s	268.366us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	2.080s	445.908us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	9.540s	2.065ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	34.730s	8.214ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	25.710s	8.465ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	34.910s	12.971ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	8.837m	128.257ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	3.420s	702.451us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	6.760s	2.626ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	5.620s	708.797us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	3.270s	396.503us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	18.540s	4.387ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.425m	13.287ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.130s	101.896us	1	1	100.00
V2	stress_all	rv_dm_stress_all	32.750s	8.026ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.740s	130.459us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	7.750s	593.233us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	7.750s	593.233us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.465m	7.932ms	5	5	100.00
		rv_dm_csr_hw_reset	4.040s	345.277us	5	5	100.00
		rv_dm_csr_rw	3.730s	254.750us	20	20	100.00
		rv_dm_same_csr_outstanding	11.150s	1.185ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.465m	7.932ms	5	5	100.00
		rv_dm_csr_hw_reset	4.040s	345.277us	5	5	100.00
		rv_dm_csr_rw	3.730s	254.750us	20	20	100.00
		rv_dm_same_csr_outstanding	11.150s	1.185ms	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	15.930s	2.863ms	5	5	100.00
		rv_dm_tl_intg_err	34.490s	3.403ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	34.490s	3.403ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	6.760s	2.626ms	2	2	100.00
		rv_dm_debug_disabled	1.450s	280.036us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	6.760s	2.626ms	2	2	100.00
		rv_dm_debug_disabled	1.450s	280.036us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	10.110s	2.461ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	4.480s	558.617us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.280s	138.996us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.280s	138.996us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	4.480s	558.617us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	2.315m	9.256ms	10	10	100.00
V3		TOTAL			10	10	100.00
	Unmapped tests	rv_dm_scanmode	1.050s	26.618us	1	1	100.00
		TOTAL			483	483	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.10	96.32	89.53	92.10	93.33	90.44	98.63	56.31

Past Results

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