RV_DM Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	8.210s	2.314ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	2.470s	1.461ms	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	3.900s	598.047us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	39.390s	39.213ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	7.100s	2.054ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	35.420s	19.840ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	44.980s	14.155ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.310m	51.756ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	2.815m	46.346ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	2.780s	423.093us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.240s	518.107us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.170s	573.444us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.810s	625.425us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.300s	182.715us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	4.870s	1.219ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.140s	274.579us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.270s	1.055ms	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	2.780s	423.093us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.040s	290.762us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.460s	366.120us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.170s	573.444us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.890s	44.098us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	3.260s	218.524us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	3.850s	185.374us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	57.560s	1.484ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.435m	4.435ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	5.960s	118.099us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.435m	4.435ms	5	5	100.00
		rv_dm_csr_rw	3.850s	185.374us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.150s	41.518us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	2.060s	183.926us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	8.210s	2.314ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.810s	319.249us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.570s	371.366us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	0.910s	125.244us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.650s	672.913us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	28.000s	7.186ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	30.280s	8.829ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	22.970s	11.489ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	3.014m	63.639ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.310s	445.250us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	9.870s	3.529ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	3.110s	773.157us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.280s	215.136us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	8.590s	8.309ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.647m	53.956ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.950s	77.529us	1	1	100.00
V2	stress_all	rv_dm_stress_all	14.680s	4.985ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.700s	152.445us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	7.080s	349.009us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	7.080s	349.009us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.435m	4.435ms	5	5	100.00
		rv_dm_csr_hw_reset	3.260s	218.524us	5	5	100.00
		rv_dm_csr_rw	3.850s	185.374us	20	20	100.00
		rv_dm_same_csr_outstanding	11.530s	483.035us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.435m	4.435ms	5	5	100.00
		rv_dm_csr_hw_reset	3.260s	218.524us	5	5	100.00
		rv_dm_csr_rw	3.850s	185.374us	20	20	100.00
		rv_dm_same_csr_outstanding	11.530s	483.035us	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	6.150s	1.682ms	5	5	100.00
		rv_dm_tl_intg_err	23.250s	4.793ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	23.250s	4.793ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	9.870s	3.529ms	2	2	100.00
		rv_dm_debug_disabled	0.910s	87.869us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	9.870s	3.529ms	2	2	100.00
		rv_dm_debug_disabled	0.910s	87.869us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	8.210s	2.314ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	2.710s	576.726us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.180s	68.814us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.180s	68.814us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	2.710s	576.726us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.399m	6.958ms	9	10	90.00
V3		TOTAL			9	10	90.00
	Unmapped tests	rv_dm_scanmode	0.710s	47.226us	1	1	100.00
		TOTAL			482	483	99.79

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.98	96.27	89.82	92.10	94.67	90.10	98.74	61.18

Failure Buckets

• UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:62) [rv_dm_mem_tl_access_resuming_vseq] Check failed dmi_status == UVM_IS_OK (* [*] vs * [*]) has 1 failures:
  • Test rv_dm_stress_all_with_rand_reset has 1 failures.

    • 6.rv_dm_stress_all_with_rand_reset.35262431976460685543329602402604378121569386464207688866077122732418654632944
      Line 163, in log /workspaces/repo/scratch/os_regression_2024_09_03/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8221143913 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed dmi_status == UVM_IS_OK (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 8221143913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.09.02_11.33.10
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• 2024.08.28_06.58.46
• 2024.08.26_02.20.16
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