RV_DM Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	5.750s	1.957ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	5.200s	719.383us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	4.210s	534.437us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	24.540s	33.790ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	8.110s	1.323ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	30.220s	14.499ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	36.540s	7.670ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.074m	88.517ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	4.851m	88.319ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	2.000s	711.394us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.150s	182.606us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	4.440s	875.670us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.640s	186.709us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.430s	139.404us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	3.270s	692.048us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.080s	67.957us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.180s	593.567us	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	2.000s	711.394us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.490s	359.919us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	3.600s	1.285ms	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	4.440s	875.670us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.440s	59.179us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	4.020s	653.652us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	4.150s	229.382us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.224m	1.502ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.351m	3.657ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	6.110s	59.150us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.351m	3.657ms	5	5	100.00
		rv_dm_csr_rw	4.150s	229.382us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.740s	120.964us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.540s	100.527us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	5.750s	1.957ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.670s	180.423us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	2.220s	796.339us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.260s	155.595us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	5.620s	2.033ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	30.100s	16.935ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	28.770s	8.926ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	18.290s	6.582ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.249m	36.432ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	3.470s	629.557us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	6.220s	1.574ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	3.490s	661.579us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.750s	129.020us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	13.160s	4.962ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.548m	13.394ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.040s	72.027us	1	1	100.00
V2	stress_all	rv_dm_stress_all	26.240s	7.536ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	2.160s	185.704us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	10.660s	665.828us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	10.660s	665.828us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.351m	3.657ms	5	5	100.00
		rv_dm_csr_hw_reset	4.020s	653.652us	5	5	100.00
		rv_dm_csr_rw	4.150s	229.382us	20	20	100.00
		rv_dm_same_csr_outstanding	14.480s	4.557ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.351m	3.657ms	5	5	100.00
		rv_dm_csr_hw_reset	4.020s	653.652us	5	5	100.00
		rv_dm_csr_rw	4.150s	229.382us	20	20	100.00
		rv_dm_same_csr_outstanding	14.480s	4.557ms	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	10.840s	2.915ms	5	5	100.00
		rv_dm_tl_intg_err	28.970s	1.956ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	28.970s	1.956ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	6.220s	1.574ms	2	2	100.00
		rv_dm_debug_disabled	1.150s	55.806us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	6.220s	1.574ms	2	2	100.00
		rv_dm_debug_disabled	1.150s	55.806us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	5.750s	1.957ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	3.890s	462.462us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.320s	67.738us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.320s	67.738us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	3.890s	462.462us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.303m	31.660ms	10	10	100.00
V3		TOTAL			10	10	100.00
	Unmapped tests	rv_dm_scanmode	0.830s	93.754us	1	1	100.00
		TOTAL			483	483	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.06	96.32	90.10	92.10	94.67	90.44	98.63	61.18

Past Results

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