RV_DM Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: 25b1acbf68

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	4.790s	1.477ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	8.140s	1.337ms	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	4.500s	761.690us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	41.830s	8.363ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	4.600s	2.370ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	24.160s	5.610ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	1.048m	14.255ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.540m	27.672ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	1.677m	118.468ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	4.750s	1.134ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	2.860s	547.780us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	3.030s	584.666us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	2.980s	395.424us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.260s	558.048us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	2.590s	1.400ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.380s	333.372us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	4.400s	1.134ms	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	4.750s	1.134ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.760s	145.730us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	2.320s	905.246us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	3.030s	584.666us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.000s	129.931us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	3.380s	426.381us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	4.110s	851.022us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.490m	10.210ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.441m	14.240ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	6.090s	226.928us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.441m	14.240ms	5	5	100.00
		rv_dm_csr_rw	4.110s	851.022us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.400s	76.962us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.180s	136.855us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	4.790s	1.477ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.670s	214.671us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.420s	637.643us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	2.740s	565.872us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	3.210s	720.283us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	28.180s	7.570ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	44.320s	14.804ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	27.650s	11.373ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	5.211m	116.382ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.980s	302.252us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	6.650s	3.792ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.790s	456.151us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.660s	117.286us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	10.820s	8.339ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.758m	22.925ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.580s	268.767us	1	1	100.00
V2	stress_all	rv_dm_stress_all	27.390s	8.636ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.630s	112.539us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	9.760s	567.056us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	9.760s	567.056us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.441m	14.240ms	5	5	100.00
		rv_dm_csr_hw_reset	3.380s	426.381us	5	5	100.00
		rv_dm_csr_rw	4.110s	851.022us	20	20	100.00
		rv_dm_same_csr_outstanding	12.870s	4.106ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.441m	14.240ms	5	5	100.00
		rv_dm_csr_hw_reset	3.380s	426.381us	5	5	100.00
		rv_dm_csr_rw	4.110s	851.022us	20	20	100.00
		rv_dm_same_csr_outstanding	12.870s	4.106ms	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	9.820s	2.471ms	5	5	100.00
		rv_dm_tl_intg_err	42.500s	6.429ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	42.500s	6.429ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	6.650s	3.792ms	2	2	100.00
		rv_dm_debug_disabled	1.330s	82.711us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	6.650s	3.792ms	2	2	100.00
		rv_dm_debug_disabled	1.330s	82.711us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	4.790s	1.477ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	2.380s	565.551us	10	10	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.460s	112.758us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.460s	112.758us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	2.380s	565.551us	10	10	100.00
V2S		TOTAL			41	41	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	2.314m	28.217ms	10	10	100.00
V3		TOTAL			10	10	100.00
	Unmapped tests	rv_dm_scanmode	0.690s	44.345us	1	1	100.00
		TOTAL			483	483	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.06	96.32	90.10	92.10	94.67	90.44	98.63	61.18

Past Results

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