RV_TIMER Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	51.095m	298.184ms	189	200	94.50
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.610s	35.946us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.640s	18.504us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.670s	1.703ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.830s	225.601us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.520s	109.244us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.640s	18.504us	20	20	100.00
		rv_timer_csr_aliasing	0.830s	225.601us	5	5	100.00
V1		TOTAL			244	255	95.69
V2	random_reset	rv_timer_random_reset	28.980m	100.301ms	50	50	100.00
V2	disabled	rv_timer_disabled	5.308m	222.097ms	50	50	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	17.912m	1.726s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	17.912m	1.726s	50	50	100.00
V2	stress	rv_timer_stress_all	1.217h	2.216s	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.610s	34.224us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.090s	65.337us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.090s	65.337us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.610s	35.946us	5	5	100.00
		rv_timer_csr_rw	0.640s	18.504us	20	20	100.00
		rv_timer_csr_aliasing	0.830s	225.601us	5	5	100.00
		rv_timer_same_csr_outstanding	0.840s	21.257us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.610s	35.946us	5	5	100.00
		rv_timer_csr_rw	0.640s	18.504us	20	20	100.00
		rv_timer_csr_aliasing	0.830s	225.601us	5	5	100.00
		rv_timer_same_csr_outstanding	0.840s	21.257us	20	20	100.00
V2		TOTAL			290	290	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.060s	258.512us	5	5	100.00
		rv_timer_tl_intg_err	1.450s	167.709us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.450s	167.709us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	29.751m	609.182ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			609	620	98.23

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	7	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.38	98.73	100.00	--	100.00	100.00	99.55

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 10 failures:

Test rv_timer_random has 10 failures.

23.rv_timer_random.2164931496
Line 218, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/23.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.rv_timer_random.696177341
Line 218, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/32.rv_timer_random/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test rv_timer_random has 1 failures.
  - 124.rv_timer_random.3061027264
    Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/124.rv_timer_random/latest/run.log
```
  Job ID: smart:fa95d14c-383d-4f31-9b2d-bbada2f99a2d
```