042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 51.337m | 1.279s | 158 | 200 | 79.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.630s | 31.389us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.580s | 24.197us | 17 | 20 | 85.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.580s | 285.144us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.780s | 37.843us | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.540s | 57.875us | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.580s | 24.197us | 17 | 20 | 85.00 |
| rv_timer_csr_aliasing | 0.780s | 37.843us | 4 | 5 | 80.00 | ||
| V1 | TOTAL | 208 | 255 | 81.57 | |||
| V2 | random_reset | rv_timer_random_reset | 24.550m | 251.676ms | 37 | 50 | 74.00 |
| V2 | disabled | rv_timer_disabled | 3.994m | 377.105ms | 38 | 50 | 76.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 23.804m | 1.681s | 37 | 50 | 74.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 23.804m | 1.681s | 37 | 50 | 74.00 |
| V2 | stress | rv_timer_stress_all | 49.929m | 1.994s | 38 | 50 | 76.00 |
| V2 | intr_test | rv_timer_intr_test | 0.610s | 25.833us | 47 | 50 | 94.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.140s | 120.743us | 18 | 20 | 90.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.140s | 120.743us | 18 | 20 | 90.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.630s | 31.389us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.580s | 24.197us | 17 | 20 | 85.00 | ||
| rv_timer_csr_aliasing | 0.780s | 37.843us | 4 | 5 | 80.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 260.554us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.630s | 31.389us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.580s | 24.197us | 17 | 20 | 85.00 | ||
| rv_timer_csr_aliasing | 0.780s | 37.843us | 4 | 5 | 80.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 260.554us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 234 | 290 | 80.69 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.900s | 86.083us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.430s | 393.638us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.430s | 393.638us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 29.208m | 436.784ms | 37 | 50 | 74.00 |
| V3 | TOTAL | 37 | 50 | 74.00 | |||
| TOTAL | 504 | 620 | 81.29 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 2 | 33.33 |
| V2 | 7 | 7 | 0 | 0.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.48 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 98.75 |
Exit reason: Error: User command failed Job returned non-zero exit code has 112 failures:
Test rv_timer_stress_all_with_rand_reset has 13 failures.
0.rv_timer_stress_all_with_rand_reset.89585939376456444225431415779052322988424399152300451409570632282657241385825
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/0.rv_timer_stress_all_with_rand_reset/latest && /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090186593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.4090186593
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
6.rv_timer_stress_all_with_rand_reset.37059199248288963173869480308136415006386330070821679903534425152136002276633
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_stress_all_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/6.rv_timer_stress_all_with_rand_reset/latest && /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044857625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.2044857625
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 11 more failures.
Test rv_timer_tl_errors has 2 failures.
0.rv_timer_tl_errors.76166583262722459055985653127046716384997156021037681446485494524228852314934
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest/run.log
[make]: simulate
cd /workspace/0.rv_timer_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378494774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2378494774
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:52 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
3.rv_timer_tl_errors.19791677390972466138693364778328572092835339874519189282437858998653064220474
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_tl_errors/latest/run.log
[make]: simulate
cd /workspace/3.rv_timer_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183985978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.4183985978
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:52 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test rv_timer_csr_rw has 3 failures.
1.rv_timer_csr_rw.82114678205661297713036827421900890242360914145343619795602983936523988884632
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_csr_rw/latest/run.log
[make]: simulate
cd /workspace/1.rv_timer_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431376536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2431376536
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:52 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
8.rv_timer_csr_rw.22407918398677182700615065724555853237499029097036423810428161343343362603213
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/8.rv_timer_csr_rw/latest/run.log
[make]: simulate
cd /workspace/8.rv_timer_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758834381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2758834381
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:52 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
Test rv_timer_random has 40 failures.
2.rv_timer_random.92171011727176658435749650287195690271192744462639502213038109886804756171564
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_random/latest/run.log
[make]: simulate
cd /workspace/2.rv_timer_random/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707145004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3707145004
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
4.rv_timer_random.105319295979286736730537590294422739287443466121122117556320872033626135018709
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_random/latest/run.log
[make]: simulate
cd /workspace/4.rv_timer_random/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608413909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2608413909
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:39 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 38 more failures.
Test rv_timer_random_reset has 13 failures.
2.rv_timer_random_reset.6934781747408423117250853761460046054663632367405042784713588403904058506778
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/2.rv_timer_random_reset/latest/run.log
[make]: simulate
cd /workspace/2.rv_timer_random_reset/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881844250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3881844250
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:39 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
4.rv_timer_random_reset.101522666956522102220051872456381520009669079624010295342591013408654786529273
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_random_reset/latest/run.log
[make]: simulate
cd /workspace/4.rv_timer_random_reset/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705923065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.705923065
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:39 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 11 more failures.
... and 7 more tests.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
9.rv_timer_disabled.64493975046976801053986646116133418819939487678523839522862365994221673825981
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rv_timer_disabled.113825187695266729683890671034485735889328219724631323787321112050428553878563
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/12.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
30.rv_timer_random.80059430233868901460413910032600317832059864829724280891772274489711610291729
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/30.rv_timer_random/latest/run.log
Job ID: smart:180b4edc-907d-41f9-a20e-697cee03f666
155.rv_timer_random.101899433994188299283785566930920713132877277675961005590693960427579278522833
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/155.rv_timer_random/latest/run.log
Job ID: smart:45188f0d-7a70-4d83-bd0f-666c71866459