cf38c1d296| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 47.094m | 1.353s | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.580s | 39.758us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.590s | 51.431us | 12 | 20 | 60.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.610s | 423.112us | 4 | 5 | 80.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.870s | 36.392us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.660s | 34.217us | 13 | 20 | 65.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.590s | 51.431us | 12 | 20 | 60.00 |
| rv_timer_csr_aliasing | 0.870s | 36.392us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 239 | 255 | 93.73 | |||
| V2 | random_reset | rv_timer_random_reset | 11.490m | 557.228ms | 48 | 50 | 96.00 |
| V2 | disabled | rv_timer_disabled | 5.546m | 783.483ms | 50 | 50 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 22.853m | 836.525ms | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 22.853m | 836.525ms | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.008h | 451.070ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.600s | 32.769us | 36 | 50 | 72.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.250s | 258.442us | 17 | 20 | 85.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.250s | 258.442us | 17 | 20 | 85.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.580s | 39.758us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.590s | 51.431us | 12 | 20 | 60.00 | ||
| rv_timer_csr_aliasing | 0.870s | 36.392us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.820s | 116.308us | 17 | 20 | 85.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.580s | 39.758us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.590s | 51.431us | 12 | 20 | 60.00 | ||
| rv_timer_csr_aliasing | 0.870s | 36.392us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.820s | 116.308us | 17 | 20 | 85.00 | ||
| V2 | TOTAL | 268 | 290 | 92.41 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.210s | 1.404ms | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.370s | 122.685us | 15 | 20 | 75.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.370s | 122.685us | 15 | 20 | 75.00 |
| V2S | TOTAL | 20 | 25 | 80.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 35.472m | 480.404ms | 50 | 50 | 100.00 |
| V3 | TOTAL | 50 | 50 | 100.00 | |||
| TOTAL | 577 | 620 | 93.06 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 3 | 50.00 |
| V2 | 7 | 7 | 3 | 42.86 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 1 | 1 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.66 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.89 |
Exit reason: Error: User command failed Job returned non-zero exit code has 41 failures:
Test rv_timer_intr_test has 14 failures.
0.rv_timer_intr_test.9111379446766785122507996479333572431866239935164270406750173656881534370278
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_intr_test/latest/run.log
[make]: simulate
cd /workspace/0.rv_timer_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660636134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.660636134
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:01 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
3.rv_timer_intr_test.36700232202912788490605824447696483903712789873909795343185451022314615343803
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_intr_test/latest/run.log
[make]: simulate
cd /workspace/3.rv_timer_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319818427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.319818427
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:01 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 12 more failures.
Test rv_timer_csr_rw has 8 failures.
0.rv_timer_csr_rw.45643781366746041394734453115985751005072913701373950994515514090895686329329
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest/run.log
[make]: simulate
cd /workspace/0.rv_timer_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152134641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.152134641
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:01 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
3.rv_timer_csr_rw.110204204642736128874120579837825745695466214766104007258791766553838873911970
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_csr_rw/latest/run.log
[make]: simulate
cd /workspace/3.rv_timer_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837540002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1837540002
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:01 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 6 more failures.
Test rv_timer_csr_mem_rw_with_rand_reset has 7 failures.
0.rv_timer_csr_mem_rw_with_rand_reset.112309360110293237854860197000846227468898115296795506164645134188105424770018
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73470946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.73470946
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:01 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
3.rv_timer_csr_mem_rw_with_rand_reset.43328690732927881331712325577902190763143059517702952721528151890092017654760
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/3.rv_timer_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249713128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1249713128
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:01 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 5 more failures.
Test rv_timer_csr_bit_bash has 1 failures.
1.rv_timer_csr_bit_bash.16850774311367529733850460141997309111310095384667268068160453615883604361127
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_csr_bit_bash/latest/run.log
[make]: simulate
cd /workspace/1.rv_timer_csr_bit_bash/latest && /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954605991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.3954605991
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:01 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test rv_timer_tl_intg_err has 5 failures.
7.rv_timer_tl_intg_err.27761110897665203218742193022512688577994187654832043052385359793146946624033
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/7.rv_timer_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101582369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.2101582369
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:01 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
9.rv_timer_tl_intg_err.105369516179593709884437985663076136581113582180391666545568218834438385404898
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_tl_intg_err/latest/run.log
[make]: simulate
cd /workspace/9.rv_timer_tl_intg_err/latest && /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937424866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.2937424866
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 13:01 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more failures.
... and 2 more tests.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
6.rv_timer_random_reset.102203585342222458389000646201853712686351647186137477045033401461007033692387
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/6.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.rv_timer_random_reset.54459136542302285065641156565983610243751161896614164190056206348445408107711
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/43.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---