5f48fbc0e7| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 44.413m | 449.873ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.600s | 95.591us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.620s | 13.739us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.140s | 423.016us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.860s | 31.227us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.600s | 34.950us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.620s | 13.739us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.860s | 31.227us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 28.905m | 200.393ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 6.167m | 1.000s | 45 | 50 | 90.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 52.094m | 6.410s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 52.094m | 6.410s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.728h | 2.460s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.620s | 15.473us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.300s | 843.420us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.300s | 843.420us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.600s | 95.591us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 13.739us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.860s | 31.227us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 130.808us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.600s | 95.591us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 13.739us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.860s | 31.227us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.840s | 130.808us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 285 | 290 | 98.28 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.970s | 86.154us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.430s | 220.796us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.430s | 220.796us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 38.133m | 496.895ms | 50 | 50 | 100.00 |
| V3 | TOTAL | 50 | 50 | 100.00 | |||
| TOTAL | 615 | 620 | 99.19 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 1 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.65 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.77 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:
4.rv_timer_disabled.45383750861734772948512057472529845753156953784815646262368613152883506937350
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/4.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_timer_disabled.15347191689529700276725214660939774210152551334583855758146461802938906388326
Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.