RV_TIMER Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: 4d88b9516c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 45.813m 254.226ms 200 200 100.00
V1 csr_hw_reset rv_timer_csr_hw_reset 0.600s 26.234us 5 5 100.00
V1 csr_rw rv_timer_csr_rw 0.650s 37.549us 20 20 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 3.220s 171.101us 5 5 100.00
V1 csr_aliasing rv_timer_csr_aliasing 0.740s 42.728us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 1.430s 101.511us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 0.650s 37.549us 20 20 100.00
rv_timer_csr_aliasing 0.740s 42.728us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 random_reset rv_timer_random_reset 23.487m 181.378ms 50 50 100.00
V2 disabled rv_timer_disabled 5.481m 729.235ms 50 50 100.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 44.994m 7.721s 50 50 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 44.994m 7.721s 50 50 100.00
V2 stress rv_timer_stress_all 1.791h 1.916s 50 50 100.00
V2 intr_test rv_timer_intr_test 0.630s 22.258us 50 50 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 2.910s 151.008us 20 20 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 2.910s 151.008us 20 20 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 0.600s 26.234us 5 5 100.00
rv_timer_csr_rw 0.650s 37.549us 20 20 100.00
rv_timer_csr_aliasing 0.740s 42.728us 5 5 100.00
rv_timer_same_csr_outstanding 0.890s 617.498us 20 20 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 0.600s 26.234us 5 5 100.00
rv_timer_csr_rw 0.650s 37.549us 20 20 100.00
rv_timer_csr_aliasing 0.740s 42.728us 5 5 100.00
rv_timer_same_csr_outstanding 0.890s 617.498us 20 20 100.00
V2 TOTAL 290 290 100.00
V2S tl_intg_err rv_timer_sec_cm 0.930s 114.062us 5 5 100.00
rv_timer_tl_intg_err 1.560s 422.056us 20 20 100.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 1.560s 422.056us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 42.402m 135.953ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 7 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.36 98.73 100.00 -- 100.00 100.00 99.66

Past Results