796f9fb805| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 41.252m | 113.290ms | 199 | 200 | 99.50 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.600s | 13.131us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.640s | 59.870us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.810s | 1.469ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.870s | 37.454us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.530s | 152.964us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.640s | 59.870us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.870s | 37.454us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 254 | 255 | 99.61 | |||
| V2 | random_reset | rv_timer_random_reset | 21.112m | 156.951ms | 49 | 50 | 98.00 |
| V2 | disabled | rv_timer_disabled | 5.396m | 200.904ms | 49 | 50 | 98.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 20.187m | 2.068s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 20.187m | 2.068s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 53.937m | 3.615s | 49 | 50 | 98.00 |
| V2 | intr_test | rv_timer_intr_test | 0.630s | 52.132us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.460s | 225.079us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.460s | 225.079us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.600s | 13.131us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.640s | 59.870us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.870s | 37.454us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 612.167us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.600s | 13.131us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.640s | 59.870us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.870s | 37.454us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 612.167us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 290 | 98.97 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.870s | 106.716us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.820s | 963.024us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.820s | 963.024us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 38.837m | 107.173ms | 50 | 50 | 100.00 |
| V3 | TOTAL | 50 | 50 | 100.00 | |||
| TOTAL | 616 | 620 | 99.35 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 4 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 1 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.57 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.32 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
Test rv_timer_random_reset has 1 failures.
14.rv_timer_random_reset.70390650373277434135439117536439282178421053395438847811690436660659047315137
Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/14.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_stress_all has 1 failures.
14.rv_timer_stress_all.15906132332009389284686047120951103506035264871284682484235122821632226182393
Line 282, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/14.rv_timer_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_disabled has 1 failures.
24.rv_timer_disabled.54432968712930024908094954678045571921767556333622498206597737235582048611385
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/24.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
31.rv_timer_random.64915176231805465610705474814444460253940127096405295752587607524180677120404
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/31.rv_timer_random/latest/run.log
Job ID: smart:a36e1b2d-d542-4cae-83ad-4a22adc00ade