17d5a97c3b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 38.173m | 166.717ms | 199 | 200 | 99.50 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.580s | 30.879us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.650s | 32.230us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.810s | 408.703us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.840s | 170.714us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.600s | 133.296us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.650s | 32.230us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.840s | 170.714us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 254 | 255 | 99.61 | |||
| V2 | random_reset | rv_timer_random_reset | 32.421m | 109.957ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 4.526m | 189.392ms | 46 | 50 | 92.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 14.990m | 551.156ms | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 14.990m | 551.156ms | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.268h | 1.045s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.610s | 16.124us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 3.140s | 149.130us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 3.140s | 149.130us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.580s | 30.879us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.650s | 32.230us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.840s | 170.714us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.860s | 34.678us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.580s | 30.879us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.650s | 32.230us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.840s | 170.714us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.860s | 34.678us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.800s | 109.240us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.590s | 121.782us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.590s | 121.782us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 42.096m | 149.819ms | 50 | 50 | 100.00 |
| V3 | TOTAL | 50 | 50 | 100.00 | |||
| TOTAL | 615 | 620 | 99.19 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 1 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.64 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.77 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
34.rv_timer_disabled.58225006396241197535002343881759619975511758781600262695223242680642926533460
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/34.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.rv_timer_disabled.98364617758161633496069644561544859046915690946716089054988251807631190688953
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/42.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
114.rv_timer_random.98403535779041099186275384218985432334629387378112451350871566881831044705556
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/114.rv_timer_random/latest/run.log
Job ID: smart:7b66a2ab-055f-498b-ae7d-ac253994d92b