4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0 | 200 | 0.00 | ||
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | rv_timer_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0 | 20 | 0.00 | ||
| rv_timer_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 255 | 0.00 | |||
| V2 | random_reset | rv_timer_random_reset | 0 | 50 | 0.00 | ||
| V2 | disabled | rv_timer_disabled | 0 | 50 | 0.00 | ||
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 0 | 50 | 0.00 | ||
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 0 | 50 | 0.00 | ||
| V2 | stress | rv_timer_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | rv_timer_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0 | 5 | 0.00 | ||
| rv_timer_csr_rw | 0 | 20 | 0.00 | ||||
| rv_timer_csr_aliasing | 0 | 5 | 0.00 | ||||
| rv_timer_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0 | 5 | 0.00 | ||
| rv_timer_csr_rw | 0 | 20 | 0.00 | ||||
| rv_timer_csr_aliasing | 0 | 5 | 0.00 | ||||
| rv_timer_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 290 | 0.00 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0 | 5 | 0.00 | ||
| rv_timer_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 620 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 7 | 7 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 622 failures:
0.rv_timer_random.111237045827625040442075763964007397983321586214573579194407706136025650961242
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_random/latest/run.log
1.rv_timer_random.61791940665357378201662757017920507727741834596892040958701382292615441406405
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_random/latest/run.log
... and 198 more failures.
0.rv_timer_disabled.94211215758716083410318654583168530794240655546723357281706090789378959125094
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_disabled/latest/run.log
1.rv_timer_disabled.76052270338797133013045579759169633879938531482755893400264282223817262426577
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_disabled/latest/run.log
... and 48 more failures.
0.rv_timer_cfg_update_on_fly.104192650399130642397529012503250336636842817272443188719922875996291700113406
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest/run.log
1.rv_timer_cfg_update_on_fly.22327523495689055597737873552236021828728261379658079817678187511362727280375
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest/run.log
... and 48 more failures.
0.rv_timer_random_reset.107811113768995572843212366382948985476969403205185079077769427636272279770982
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
1.rv_timer_random_reset.108103999740479007344983517128243169881589938221266896804797887227532003948000
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
... and 48 more failures.
0.rv_timer_stress_all_with_rand_reset.51584673912847078359803153635493306916589630824560989415392042994972414255725
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
1.rv_timer_stress_all_with_rand_reset.4273530980686575884606592482821593922573227845446057159385167670949761341078
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
... and 48 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.