RV_TIMER Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: 0dd29ab736

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 random rv_timer_random 52.488m 152.505ms 200 200 100.00
V1 csr_hw_reset rv_timer_csr_hw_reset 0.680s 74.414us 5 5 100.00
V1 csr_rw rv_timer_csr_rw 0.710s 17.300us 20 20 100.00
V1 csr_bit_bash rv_timer_csr_bit_bash 3.200s 313.937us 5 5 100.00
V1 csr_aliasing rv_timer_csr_aliasing 0.890s 57.398us 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_timer_csr_mem_rw_with_rand_reset 1.590s 32.155us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_timer_csr_rw 0.710s 17.300us 20 20 100.00
rv_timer_csr_aliasing 0.890s 57.398us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 random_reset rv_timer_random_reset 32.192m 307.508ms 50 50 100.00
V2 disabled rv_timer_disabled 6.275m 238.810ms 50 50 100.00
V2 cfg_update_on_fly rv_timer_cfg_update_on_fly 21.101m 2.418s 50 50 100.00
V2 no_interrupt_test rv_timer_cfg_update_on_fly 21.101m 2.418s 50 50 100.00
V2 stress rv_timer_stress_all 1.936h 2.708s 50 50 100.00
V2 intr_test rv_timer_intr_test 0.650s 35.433us 50 50 100.00
V2 tl_d_oob_addr_access rv_timer_tl_errors 3.430s 258.677us 20 20 100.00
V2 tl_d_illegal_access rv_timer_tl_errors 3.430s 258.677us 20 20 100.00
V2 tl_d_outstanding_access rv_timer_csr_hw_reset 0.680s 74.414us 5 5 100.00
rv_timer_csr_rw 0.710s 17.300us 20 20 100.00
rv_timer_csr_aliasing 0.890s 57.398us 5 5 100.00
rv_timer_same_csr_outstanding 0.900s 64.402us 20 20 100.00
V2 tl_d_partial_access rv_timer_csr_hw_reset 0.680s 74.414us 5 5 100.00
rv_timer_csr_rw 0.710s 17.300us 20 20 100.00
rv_timer_csr_aliasing 0.890s 57.398us 5 5 100.00
rv_timer_same_csr_outstanding 0.900s 64.402us 20 20 100.00
V2 TOTAL 290 290 100.00
V2S tl_intg_err rv_timer_sec_cm 0.910s 325.083us 5 5 100.00
rv_timer_tl_intg_err 1.590s 401.244us 20 20 100.00
V2S sec_cm_bus_integrity rv_timer_tl_intg_err 1.590s 401.244us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_timer_stress_all_with_rand_reset 25.276m 945.452ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 620 620 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 7 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.55 99.36 98.73 100.00 -- 100.00 100.00 99.21

Past Results