RV_TIMER Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: 5c87d18988

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	38.206m	595.152ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.610s	20.880us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.610s	11.748us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.720s	1.428ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.890s	301.684us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.630s	38.672us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.610s	11.748us	20	20	100.00
		rv_timer_csr_aliasing	0.890s	301.684us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	28.948m	178.422ms	50	50	100.00
V2	disabled	rv_timer_disabled	4.846m	189.347ms	50	50	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	25.790m	2.657s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	25.790m	2.657s	50	50	100.00
V2	stress	rv_timer_stress_all	1.848h	771.120ms	49	50	98.00
V2	intr_test	rv_timer_intr_test	0.620s	11.724us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.650s	188.362us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.650s	188.362us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.610s	20.880us	5	5	100.00
		rv_timer_csr_rw	0.610s	11.748us	20	20	100.00
		rv_timer_csr_aliasing	0.890s	301.684us	5	5	100.00
		rv_timer_same_csr_outstanding	0.850s	141.445us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.610s	20.880us	5	5	100.00
		rv_timer_csr_rw	0.610s	11.748us	20	20	100.00
		rv_timer_csr_aliasing	0.890s	301.684us	5	5	100.00
		rv_timer_same_csr_outstanding	0.850s	141.445us	20	20	100.00
V2		TOTAL			289	290	99.66
V2S	tl_intg_err	rv_timer_sec_cm	0.900s	654.343us	5	5	100.00
		rv_timer_tl_intg_err	1.460s	429.223us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.460s	429.223us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	29.118m	103.642ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			619	620	99.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.66	99.36	98.73	100.00	--	100.00	100.00	99.89

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test rv_timer_stress_all has 1 failures.

    • 9.rv_timer_stress_all.67657633120852767853666960555538445389802466271255448457596610494483930097515
      Line 276, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/9.rv_timer_stress_all/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.02.05_04.47.46
• 2024.01.31_20.59.14
• 2024.01.25_17.54.31
• 2024.01.22_11.07.05
• 2024.01.18_08.47.32
• 2024.01.15_04.05.42