93b7cb99d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0 | 200 | 0.00 | ||
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | rv_timer_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0 | 20 | 0.00 | ||
| rv_timer_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 255 | 0.00 | |||
| V2 | random_reset | rv_timer_random_reset | 0 | 50 | 0.00 | ||
| V2 | disabled | rv_timer_disabled | 0 | 50 | 0.00 | ||
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 0 | 50 | 0.00 | ||
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 0 | 50 | 0.00 | ||
| V2 | stress | rv_timer_stress_all | 0 | 50 | 0.00 | ||
| V2 | intr_test | rv_timer_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0 | 5 | 0.00 | ||
| rv_timer_csr_rw | 0 | 20 | 0.00 | ||||
| rv_timer_csr_aliasing | 0 | 5 | 0.00 | ||||
| rv_timer_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0 | 5 | 0.00 | ||
| rv_timer_csr_rw | 0 | 20 | 0.00 | ||||
| rv_timer_csr_aliasing | 0 | 5 | 0.00 | ||||
| rv_timer_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 290 | 0.00 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0 | 5 | 0.00 | ||
| rv_timer_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 620 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 7 | 7 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 622 failures:
0.rv_timer_random.39724571326777114333203261209256040593625990613929130536463420611491417489232
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_random/latest/run.log
1.rv_timer_random.41690180352660928064168624204418439454578218883661576922638829168391117685261
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_random/latest/run.log
... and 198 more failures.
0.rv_timer_disabled.65044109776527161984082239732628557926305816096819545771234466987792156094459
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_disabled/latest/run.log
1.rv_timer_disabled.115273643230887224633017881946962678837429374731250245016938738778654888246044
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_disabled/latest/run.log
... and 48 more failures.
0.rv_timer_cfg_update_on_fly.107768859108253008579370029973277824780071409735733673012909201217229886523963
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest/run.log
1.rv_timer_cfg_update_on_fly.733125587216365541633182631249660120873125116208426141726458512898055941378
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest/run.log
... and 48 more failures.
0.rv_timer_random_reset.66700197407054426900552640728711803008392527223368586697249162247003749604397
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
1.rv_timer_random_reset.98211252101894765102353137288628373462672101170059531542242370443078036629585
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
... and 48 more failures.
0.rv_timer_stress_all_with_rand_reset.66893482724981739847501743613826927021701589820874628521118603254283292911704
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
1.rv_timer_stress_all_with_rand_reset.13915534390300235553516032516944845820805981765392824001455853741546562725872
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
... and 48 more failures.
Job rv_timer-sim-vcs_build_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
default
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/default/build.log
Job ID: smart:a0f42305-9d6a-4e3e-9c00-404e8da081fb
Job rv_timer-sim-vcs_build_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
cover_reg_top
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/cover_reg_top/build.log
Job ID: smart:6e13f50e-fcbe-47e9-8e7b-7fd0332b3f8b