bbf435ceff| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 37.883m | 408.901ms | 199 | 200 | 99.50 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.590s | 57.916us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.620s | 122.821us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.130s | 175.974us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.830s | 500.668us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.300s | 32.355us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.620s | 122.821us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.830s | 500.668us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 254 | 255 | 99.61 | |||
| V2 | random_reset | rv_timer_random_reset | 15.598m | 91.461ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 4.877m | 201.861ms | 48 | 50 | 96.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 17.334m | 622.467ms | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 17.334m | 622.467ms | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.054h | 796.547ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.620s | 19.153us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.580s | 1.288ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.580s | 1.288ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.590s | 57.916us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 122.821us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.830s | 500.668us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.800s | 152.150us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.590s | 57.916us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 122.821us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.830s | 500.668us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.800s | 152.150us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 290 | 99.31 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.970s | 154.937us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.470s | 186.621us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.470s | 186.621us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 26.726m | 334.435ms | 14 | 50 | 28.00 |
| V3 | TOTAL | 14 | 50 | 28.00 | |||
| TOTAL | 581 | 620 | 93.71 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.61 | 99.36 | 98.73 | 100.00 | -- | 100.00 | 100.00 | 99.55 |
UVM_ERROR (cip_base_vseq.sv:836) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
0.rv_timer_stress_all_with_rand_reset.56840360263119239275489094162067095513552661908027456344372122090590919174277
Line 671, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 192027775729 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 192027775729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.55542205764193357142754782177446304871763493080451386742874341715513034152845
Line 311, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25348847224 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 25348847224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 34 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
14.rv_timer_disabled.27942649527748130794210124878599337133398247304518813553617528381825213854419
Line 250, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/14.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.rv_timer_disabled.54764329760721804438708608330613494192618539822774880443495510793406934262179
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/47.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rv_timer-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
115.rv_timer_random.53565480047701360994800247738081433406127668203075752801344604225147132502861
Log /container/opentitan-public/scratch/os_regression/rv_timer-sim-vcs/115.rv_timer_random/latest/run.log
Job ID: smart:14f2e452-957e-4d56-aa18-6395f6b18f7d