RV_TIMER Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	49.290m	106.737ms	199	200	99.50
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.810s	17.660us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.820s	40.632us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.380s	2.361ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.110s	195.348us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.510s	27.984us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.820s	40.632us	20	20	100.00
		rv_timer_csr_aliasing	1.110s	195.348us	5	5	100.00
V1		TOTAL			254	255	99.61
V2	random_reset	rv_timer_random_reset	13.403m	164.295ms	50	50	100.00
V2	disabled	rv_timer_disabled	7.540m	888.058ms	47	50	94.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	30.060m	4.837s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	30.060m	4.837s	50	50	100.00
V2	stress	rv_timer_stress_all	1.347h	866.403ms	49	50	98.00
V2	intr_test	rv_timer_intr_test	0.770s	47.004us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.130s	203.671us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.130s	203.671us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.810s	17.660us	5	5	100.00
		rv_timer_csr_rw	0.820s	40.632us	20	20	100.00
		rv_timer_csr_aliasing	1.110s	195.348us	5	5	100.00
		rv_timer_same_csr_outstanding	0.950s	74.173us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.810s	17.660us	5	5	100.00
		rv_timer_csr_rw	0.820s	40.632us	20	20	100.00
		rv_timer_csr_aliasing	1.110s	195.348us	5	5	100.00
		rv_timer_same_csr_outstanding	0.950s	74.173us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	rv_timer_sec_cm	1.430s	1.539ms	5	5	100.00
		rv_timer_tl_intg_err	1.490s	408.639us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.490s	408.639us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.288m	9.137ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			585	620	94.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	5	71.43
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.64	99.36	99.04	100.00	--	100.00	100.00	99.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test rv_timer_stress_all_with_rand_reset has 29 failures.
  - 0.rv_timer_stress_all_with_rand_reset.4128429025957387441357210441569462772356336972814891807515470534243331230153
    Line 234, in log /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12984287971 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12984287971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rv_timer_stress_all_with_rand_reset.107793431529850641566322275505399519666016246090609837498419889428272560548697
    Line 119, in log /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1474386016 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1474386016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test rv_timer_stress_all has 1 failures.
  - 20.rv_timer_stress_all.1633634868547088654523102515626264097587222675367334630549224383293884950801
    Line 88, in log /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/20.rv_timer_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_timer_disabled has 3 failures.
  - 31.rv_timer_disabled.95796065061921842052779362527992782344575192172598538462338140640432175075867
    Line 63, in log /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/31.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.rv_timer_disabled.78242163726258289605630189505648323636510322357945214897283131990290506888696
    Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/41.rv_timer_disabled/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 33.rv_timer_stress_all_with_rand_reset.9620339310722416900262328321719101157888112655679241031903538077241887274487
    Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/33.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1018674497 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1018674497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test rv_timer_random has 1 failures.
  - 110.rv_timer_random.106936336785539265556955084610455506136434751905609272984231580132990629460603
    Log /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/110.rv_timer_random/latest/run.log
```
  Job timed out after 60 minutes
```

RV_TIMER Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `372a6306e0`