af2d1709f9| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 54.921m | 301.710ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.590s | 29.652us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.620s | 14.630us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 3.510s | 426.932us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.770s | 33.453us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.480s | 595.520us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.620s | 14.630us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 0.770s | 33.453us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 27.300m | 231.065ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 7.190m | 708.452ms | 49 | 50 | 98.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 23.741m | 1.802s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 23.741m | 1.802s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.668h | 738.392ms | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.600s | 38.682us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.530s | 147.975us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.530s | 147.975us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.590s | 29.652us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 14.630us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.770s | 33.453us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 44.592us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.590s | 29.652us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.620s | 14.630us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 0.770s | 33.453us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.850s | 44.592us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 289 | 290 | 99.66 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.300s | 60.382us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 1.290s | 124.835us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.290s | 124.835us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 1.369m | 6.666ms | 12 | 50 | 24.00 |
| V3 | TOTAL | 12 | 50 | 24.00 | |||
| TOTAL | 581 | 620 | 93.71 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.72 | 99.36 | 99.04 | 100.00 | -- | 100.00 | 100.00 | 99.89 |
UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
0.rv_timer_stress_all_with_rand_reset.84733399111916934717404432315798246847274295648549656463151073107657881486883
Line 102, in log /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3434118426 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3434118426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.95221219362877870698639220764778492222615659498015342449999501515821031716633
Line 70, in log /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2306793615 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2306793615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 33 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
22.rv_timer_stress_all_with_rand_reset.53810538894134270018108791809120998659945401056865797626653924030648434217934
Line 84, in log /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/22.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3854018485 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3854018485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.rv_timer_stress_all_with_rand_reset.108640701019936720410308911003178584761217053817906081426302614240170573047332
Line 128, in log /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/28.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8518280987 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 8518280987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
8.rv_timer_disabled.45529023793779198666910316738870642619748296071064028701328536902574591869001
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_08/rv_timer-sim-vcs/8.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---