25b1acbf68| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 44.653m | 122.288ms | 200 | 200 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.890s | 28.654us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.910s | 23.575us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 4.500s | 89.877us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 1.130s | 17.132us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.740s | 54.129us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.910s | 23.575us | 20 | 20 | 100.00 |
| rv_timer_csr_aliasing | 1.130s | 17.132us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 255 | 255 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 28.233m | 140.702ms | 50 | 50 | 100.00 |
| V2 | disabled | rv_timer_disabled | 7.109m | 163.496ms | 46 | 50 | 92.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 41.838m | 7.922s | 50 | 50 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 41.838m | 7.922s | 50 | 50 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.400h | 1.133s | 50 | 50 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.880s | 18.769us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 4.140s | 219.602us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 4.140s | 219.602us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.890s | 28.654us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.910s | 23.575us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.130s | 17.132us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.260s | 40.225us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.890s | 28.654us | 5 | 5 | 100.00 |
| rv_timer_csr_rw | 0.910s | 23.575us | 20 | 20 | 100.00 | ||
| rv_timer_csr_aliasing | 1.130s | 17.132us | 5 | 5 | 100.00 | ||
| rv_timer_same_csr_outstanding | 1.260s | 40.225us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.860s | 212.560us | 5 | 5 | 100.00 |
| rv_timer_tl_intg_err | 2.160s | 225.705us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 2.160s | 225.705us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 1.371m | 5.949ms | 13 | 50 | 26.00 |
| V3 | TOTAL | 13 | 50 | 26.00 | |||
| TOTAL | 579 | 620 | 93.39 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 6 | 85.71 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.72 | 99.36 | 99.04 | 100.00 | -- | 100.00 | 100.00 | 99.89 |
UVM_ERROR (cip_base_vseq.sv:867) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
0.rv_timer_stress_all_with_rand_reset.112242379040549911172469882728506702409563147109248456575669256265537061402546
Line 72, in log /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 876192168 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 876192168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_timer_stress_all_with_rand_reset.98479608122583246598192137175132874244260081058471753894317871533946066132962
Line 180, in log /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4327609859 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10021 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4327609859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 34 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
10.rv_timer_disabled.41007220932318438372107815367129787195598006837269472295525313866552251694233
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/10.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.rv_timer_disabled.11204907289170113735784732730287809400353411600461779235658790239000947737206
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/19.rv_timer_disabled/latest/run.log
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
4.rv_timer_stress_all_with_rand_reset.68854031556481672290283782335901602572029604981007669748780148830425000361223
Line 173, in log /workspaces/repo/scratch/os_regression_2024_09_10/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9158328327 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 9158328327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---