SPI_DEVICE Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke	1.380s	254.679us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.470s	191.727us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.790s	127.844us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	40.750s	11.923ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	19.340s	2.808ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.490s	500.676us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.790s	127.844us	20	20	100.00
		spi_device_csr_aliasing	19.340s	2.808ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	13.230s	2.393ms	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	6.670s	4.705ms	5	5	100.00
V1		TOTAL			115	115	100.00
V2	base_random_seq	spi_device_txrx	43.201m	86.609ms	50	50	100.00
V2	fifo_full	spi_device_fifo_full	55.307m	60.192ms	50	50	100.00
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	45.362m	1.428s	47	50	94.00
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	46.245m	114.467ms	49	50	98.00
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	46.245m	114.467ms	49	50	98.00
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	0.800s	113.316us	50	50	100.00
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	0.960s	160.056us	50	50	100.00
V2	interrupts	spi_device_intr	1.860m	26.877ms	49	50	98.00
V2	abort	spi_device_abort	0.800s	14.227us	50	50	100.00
V2	byte_transfer_on_spi	spi_device_byte_transfer	3.790s	329.426us	50	50	100.00
V2	rx_timeout	spi_device_rx_timeout	7.140s	1.008ms	50	50	100.00
V2	bit_transfer_on_spi	spi_device_bit_transfer	3.250s	1.211ms	50	50	100.00
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	1.235h	106.333ms	50	50	100.00
V2	perf	spi_device_perf	33.043m	58.556ms	50	50	100.00
V2	csb_read	spi_device_csb_read	0.830s	27.493us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	34.203us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	18.684us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	15.090s	753.130us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	15.090s	753.130us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	42.980s	62.921ms	50	50	100.00
		spi_device_tpm_sts_read	1.140s	240.148us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.070m	11.908ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	43.890s	66.296ms	50	50	100.00
		spi_device_flash_all	5.370m	68.961ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	39.350s	14.995ms	50	50	100.00
		spi_device_flash_all	5.370m	68.961ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	39.350s	14.995ms	50	50	100.00
		spi_device_flash_all	5.370m	68.961ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.370m	68.961ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	11.940s	3.351ms	50	50	100.00
		spi_device_flash_all	5.370m	68.961ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	11.940s	3.351ms	50	50	100.00
		spi_device_flash_all	5.370m	68.961ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	11.940s	3.351ms	50	50	100.00
		spi_device_flash_all	5.370m	68.961ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	11.940s	3.351ms	50	50	100.00
		spi_device_flash_all	5.370m	68.961ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	36.690s	52.601ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	51.670s	19.640ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	51.670s	19.640ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	51.670s	19.640ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	46.090s	9.539ms	47	50	94.00
		spi_device_read_buffer_direct	7.300s	3.327ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	51.670s	19.640ms	50	50	100.00
		spi_device_flash_all	5.370m	68.961ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.370m	68.961ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.370m	68.961ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	15.430s	17.464ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	15.430s	17.464ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.695m	203.497ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.706m	565.367ms	47	50	94.00
V2	stress_all	spi_device_stress_all	1.322h	251.745ms	23	50	46.00
V2	alert_test	spi_device_alert_test	0.790s	18.601us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	49.206us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.640s	74.183us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.640s	74.183us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.470s	191.727us	5	5	100.00
		spi_device_csr_rw	2.790s	127.844us	20	20	100.00
		spi_device_csr_aliasing	19.340s	2.808ms	5	5	100.00
		spi_device_same_csr_outstanding	4.440s	773.258us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.470s	191.727us	5	5	100.00
		spi_device_csr_rw	2.790s	127.844us	20	20	100.00
		spi_device_csr_aliasing	19.340s	2.808ms	5	5	100.00
		spi_device_same_csr_outstanding	4.440s	773.258us	20	20	100.00
V2		TOTAL			1641	1680	97.68
V2S	tl_intg_err	spi_device_sec_cm	1.190s	165.807us	5	5	100.00
		spi_device_tl_intg_err	22.390s	818.650us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.390s	818.650us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1781	1820	97.86

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	36	36	29	80.56
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.95	99.01	96.24	98.63	92.06	97.95	96.16	98.59

Failure Buckets

UVM_ERROR (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch has 24 failures:

Test spi_device_stress_all has 24 failures.

0.spi_device_stress_all.2766387539
Line 306, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 34728111274 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x7a [1111010] vs 0x99 [10011001]) addr 0x6ebf5bbc read out mismatch
  UVM_ERROR @ 34728111274 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xbc [10111100] vs 0x96 [10010110]) addr 0x6ebf5bbd read out mismatch
  UVM_ERROR @ 34728111274 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x7e [1111110] vs 0x5e [1011110]) addr 0x6ebf5bbe read out mismatch
  UVM_ERROR @ 34728111274 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xd7 [11010111] vs 0xc4 [11000100]) addr 0x6ebf5bbf read out mismatch
  UVM_ERROR @ 34728131274 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x58 [1011000] vs 0xdf [11011111]) addr 0x6ebf5bc0 read out mismatch

2.spi_device_stress_all.719481005
Line 233, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/2.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 44345405910 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xfd [11111101] vs 0x2e [101110]) addr 0x567a7eb0 read out mismatch
  UVM_ERROR @ 44345405910 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x83 [10000011] vs 0xb4 [10110100]) addr 0x567a7eb1 read out mismatch
  UVM_ERROR @ 44345405910 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xee [11101110] vs 0x3 [11]) addr 0x567a7eb2 read out mismatch
  UVM_ERROR @ 44345405910 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xee [11101110] vs 0x93 [10010011]) addr 0x567a7eb3 read out mismatch
  UVM_ERROR @ 44347900688 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xa [1010] vs 0x2e [101110]) addr 0x567a7eb0 read out mismatch

... and 22 more failures.

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 3 failures:

Test spi_device_flash_and_tpm_min_idle has 2 failures.

9.spi_device_flash_and_tpm_min_idle.2940003824
Line 232, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_WARNING @ 5158890530 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 5158890530 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 5158890530 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 5158890530 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 5158890530 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

11.spi_device_flash_and_tpm_min_idle.2686456073
Line 223, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_WARNING @ 99627598376 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 99627598376 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 99627598376 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 99627598376 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 99627598376 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

Test spi_device_stress_all has 1 failures.

45.spi_device_stress_all.3899532591
Line 229, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/45.spi_device_stress_all/latest/run.log

  UVM_WARNING @ 72945660375 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_full" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 72945660375 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 72945660375 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_tx_watermark" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 72945660375 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_error" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 72945660375 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "generic_rx_overflow" while containing register "spi_device_reg_block.intr_state" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

Offending '(!dst_pulse_o)' has 3 failures:

Test spi_device_fifo_underflow_overflow has 2 failures.

27.spi_device_fifo_underflow_overflow.1673656571
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/27.spi_device_fifo_underflow_overflow/latest/run.log

      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 2528922242 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
  "../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 2564165936ps failed at 2564176574ps
      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 2564176574 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A

37.spi_device_fifo_underflow_overflow.2038830097
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/37.spi_device_fifo_underflow_overflow/latest/run.log

      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 247048529 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
  "../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 267432347ps failed at 267442448ps
      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 267442448 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A

Test spi_device_stress_all has 1 failures.

48.spi_device_stress_all.1751671656
Line 220, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/48.spi_device_stress_all/latest/run.log

      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 8600759791 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
  "../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv", 96: tb.dut.u_rxf_overflow.DstPulseCheck_A: started at 16498060233ps failed at 16498103711ps
      Offending '(!dst_pulse_o)'
  UVM_ERROR @ 16498103711 ps: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test spi_device_fifo_underflow_overflow has 1 failures.
  - 12.spi_device_fifo_underflow_overflow.1482520911
    Line 221, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/12.spi_device_fifo_underflow_overflow/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_device_dummy_item_extra_dly has 1 failures.
  - 43.spi_device_dummy_item_extra_dly.3598470984
    Line 218, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/43.spi_device_dummy_item_extra_dly/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:1071) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

12.spi_device_flash_and_tpm_min_idle.1749083326
Line 226, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 1520387386 ps: (spi_device_scoreboard.sv:1071) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 1549466154 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 7/7
  UVM_INFO @ 1744770566 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 5/20
  UVM_INFO @ 1904669822 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 6/20
  UVM_INFO @ 2069400002 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 7/20

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.status.txf_full reset value: * has 1 failures:

Test spi_device_intr has 1 failures.

19.spi_device_intr.1720067783
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/19.spi_device_intr/latest/run.log

  UVM_ERROR @ 1463128078 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.txf_full reset value: 0x0
  UVM_INFO @ 1671249082 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]
  Testing RxFwModeErr
  UVM_INFO @ 1671764233 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]
  Testing RxFifoFull

UVM_ERROR (spi_device_scoreboard.sv:1071) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 21.spi_device_flash_mode.248053898
    Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/21.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 15230898977 ps: (spi_device_scoreboard.sv:1071) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 16153120282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (spi_device_scoreboard.sv:1071) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 22.spi_device_flash_mode.4254195893
    Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/22.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 1783195009 ps: (spi_device_scoreboard.sv:1071) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 5846079840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:365) [spi_device_intr_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 1 failures:

Test spi_device_stress_all has 1 failures.

24.spi_device_stress_all.1711165654
Line 224, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/24.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 4753906221 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 4754006221 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 4756296221 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
  UVM_ERROR @ 4757156221 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 16 [0x10])
  UVM_ERROR @ 4757216221 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0

UVM_ERROR (spi_device_scoreboard.sv:1071) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare CmdFifoNotEmpty mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_and_tpm has 1 failures.
  - 26.spi_device_flash_and_tpm.232758516
    Line 231, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/26.spi_device_flash_and_tpm/latest/run.log
```
  UVM_ERROR @ 14476176436 ps: (spi_device_scoreboard.sv:1071) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare CmdFifoNotEmpty mismatch, act (0x0) != exp 1
  UVM_INFO @ 16837020043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (spi_device_scoreboard.sv:880) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 29.spi_device_flash_mode.2249873490
    Line 215, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/29.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 51331647305 ps: (spi_device_scoreboard.sv:880) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 51331647305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```