042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_smoke | 1.270s | 277.368us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 1.460s | 193.260us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 2.630s | 2.234ms | 15 | 20 | 75.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 40.890s | 16.685ms | 3 | 5 | 60.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 23.550s | 362.139us | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 2.680s | 70.315us | 14 | 20 | 70.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 2.630s | 2.234ms | 15 | 20 | 75.00 |
| spi_device_csr_aliasing | 23.550s | 362.139us | 4 | 5 | 80.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 13.780s | 392.370us | 4 | 5 | 80.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 5.130s | 692.053us | 5 | 5 | 100.00 |
| V1 | TOTAL | 100 | 115 | 86.96 | |||
| V2 | base_random_seq | spi_device_txrx | 27.927m | 169.825ms | 50 | 50 | 100.00 |
| V2 | fifo_full | spi_device_fifo_full | 53.165m | 525.699ms | 50 | 50 | 100.00 |
| V2 | fifo_underflow_overflow | spi_device_fifo_underflow_overflow | 23.352m | 610.198ms | 50 | 50 | 100.00 |
| V2 | dummy_sck_and_dummy_csb | spi_device_dummy_item_extra_dly | 40.054m | 110.781ms | 50 | 50 | 100.00 |
| V2 | extra_delay_on_spi | spi_device_dummy_item_extra_dly | 40.054m | 110.781ms | 50 | 50 | 100.00 |
| V2 | tx_async_fifo_reset | spi_device_tx_async_fifo_reset | 0.830s | 73.188us | 50 | 50 | 100.00 |
| V2 | rx_async_fifo_reset | spi_device_rx_async_fifo_reset | 0.980s | 151.831us | 48 | 50 | 96.00 |
| V2 | interrupts | spi_device_intr | 1.700m | 22.654ms | 48 | 50 | 96.00 |
| V2 | abort | spi_device_abort | 0.800s | 86.599us | 50 | 50 | 100.00 |
| V2 | byte_transfer_on_spi | spi_device_byte_transfer | 3.620s | 622.622us | 50 | 50 | 100.00 |
| V2 | rx_timeout | spi_device_rx_timeout | 6.960s | 7.375ms | 50 | 50 | 100.00 |
| V2 | bit_transfer_on_spi | spi_device_bit_transfer | 3.350s | 295.615us | 50 | 50 | 100.00 |
| V2 | extreme_fifo_setting | spi_device_extreme_fifo_size | 1.119h | 177.536ms | 50 | 50 | 100.00 |
| V2 | perf | spi_device_perf | 47.961m | 224.485ms | 50 | 50 | 100.00 |
| V2 | csb_read | spi_device_csb_read | 0.840s | 61.384us | 50 | 50 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 1.110s | 57.794us | 20 | 20 | 100.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.760s | 26.749us | 20 | 20 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 8.320s | 3.308ms | 50 | 50 | 100.00 |
| V2 | tpm_write | spi_device_tpm_rw | 8.320s | 3.308ms | 50 | 50 | 100.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 35.620s | 22.543ms | 50 | 50 | 100.00 |
| spi_device_tpm_sts_read | 1.280s | 189.988us | 50 | 50 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 3.299m | 45.380ms | 50 | 50 | 100.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 40.100s | 55.115ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 7.655m | 103.597ms | 47 | 50 | 94.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 39.730s | 8.209ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 7.655m | 103.597ms | 47 | 50 | 94.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 39.730s | 8.209ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 7.655m | 103.597ms | 47 | 50 | 94.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 7.655m | 103.597ms | 47 | 50 | 94.00 |
| V2 | cmd_read_status | spi_device_intercept | 15.020s | 7.975ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 7.655m | 103.597ms | 47 | 50 | 94.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 15.020s | 7.975ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 7.655m | 103.597ms | 47 | 50 | 94.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 15.020s | 7.975ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 7.655m | 103.597ms | 47 | 50 | 94.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 15.020s | 7.975ms | 50 | 50 | 100.00 |
| spi_device_flash_all | 7.655m | 103.597ms | 47 | 50 | 94.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 39.430s | 24.533ms | 50 | 50 | 100.00 |
| V2 | mailbox_command | spi_device_mailbox | 1.116m | 27.212ms | 49 | 50 | 98.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 1.116m | 27.212ms | 49 | 50 | 98.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 1.116m | 27.212ms | 49 | 50 | 98.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 1.010m | 48.851ms | 47 | 50 | 94.00 |
| spi_device_read_buffer_direct | 8.770s | 1.899ms | 50 | 50 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 1.116m | 27.212ms | 49 | 50 | 98.00 |
| spi_device_flash_all | 7.655m | 103.597ms | 47 | 50 | 94.00 | ||
| V2 | quad_spi | spi_device_flash_all | 7.655m | 103.597ms | 47 | 50 | 94.00 |
| V2 | dual_spi | spi_device_flash_all | 7.655m | 103.597ms | 47 | 50 | 94.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 15.450s | 18.767ms | 48 | 50 | 96.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 15.450s | 18.767ms | 48 | 50 | 96.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 15.525m | 489.959ms | 43 | 50 | 86.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 9.016m | 94.000ms | 47 | 50 | 94.00 |
| V2 | stress_all | spi_device_stress_all | 2.512h | 1.294s | 41 | 50 | 82.00 |
| V2 | alert_test | spi_device_alert_test | 0.810s | 29.101us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.790s | 15.695us | 40 | 50 | 80.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 5.290s | 770.936us | 16 | 20 | 80.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 5.290s | 770.936us | 16 | 20 | 80.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 1.460s | 193.260us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.630s | 2.234ms | 15 | 20 | 75.00 | ||
| spi_device_csr_aliasing | 23.550s | 362.139us | 4 | 5 | 80.00 | ||
| spi_device_same_csr_outstanding | 4.330s | 226.033us | 17 | 20 | 85.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 1.460s | 193.260us | 5 | 5 | 100.00 |
| spi_device_csr_rw | 2.630s | 2.234ms | 15 | 20 | 75.00 | ||
| spi_device_csr_aliasing | 23.550s | 362.139us | 4 | 5 | 80.00 | ||
| spi_device_same_csr_outstanding | 4.330s | 226.033us | 17 | 20 | 85.00 | ||
| V2 | TOTAL | 1631 | 1680 | 97.08 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 1.250s | 318.503us | 5 | 5 | 100.00 |
| spi_device_tl_intg_err | 23.500s | 2.299ms | 17 | 20 | 85.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 23.500s | 2.299ms | 17 | 20 | 85.00 |
| V2S | TOTAL | 22 | 25 | 88.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 1753 | 1820 | 96.32 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 3 | 37.50 |
| V2 | 36 | 36 | 24 | 66.67 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.10 | 99.01 | 96.33 | 98.63 | 92.06 | 98.05 | 95.86 | 99.76 |
Exit reason: Error: User command failed Job returned non-zero exit code has 34 failures:
Test spi_device_csr_rw has 5 failures.
0.spi_device_csr_rw.42561641852036640371481116986357903965534894461872124376749689634324694653511
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_csr_rw/latest/run.log
[make]: simulate
cd /workspace/0.spi_device_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941292615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3941292615
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:32 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
4.spi_device_csr_rw.98674352280291889705957524612171560901706120774635396970368825310160434498083
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/4.spi_device_csr_rw/latest/run.log
[make]: simulate
cd /workspace/4.spi_device_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204999203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.204999203
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more failures.
Test spi_device_csr_bit_bash has 2 failures.
0.spi_device_csr_bit_bash.96996305416781548932625044992855124487804933274897188231860240727592136043267
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_csr_bit_bash/latest/run.log
[make]: simulate
cd /workspace/0.spi_device_csr_bit_bash/latest && /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322398979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.322398979
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
2.spi_device_csr_bit_bash.115784389946731119897302268392603949391239604601039889761986190085911288543754
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/2.spi_device_csr_bit_bash/latest/run.log
[make]: simulate
cd /workspace/2.spi_device_csr_bit_bash/latest && /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156643338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.1156643338
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test spi_device_tl_errors has 3 failures.
1.spi_device_tl_errors.27914436313402913656714741694183367598879489094720162012984948893829325528126
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_tl_errors/latest/run.log
[make]: simulate
cd /workspace/1.spi_device_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294764094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3294764094
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
9.spi_device_tl_errors.46628020086640558996480343595886100701727088626209268014697646819206664758389
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/9.spi_device_tl_errors/latest/run.log
[make]: simulate
cd /workspace/9.spi_device_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536186997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2536186997
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:36 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
Test spi_device_mem_walk has 1 failures.
2.spi_device_mem_walk.13922352928298441182212928392216847302828199540251238817355314152734320849816
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/2.spi_device_mem_walk/latest/run.log
[make]: simulate
cd /workspace/2.spi_device_mem_walk/latest && /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414544792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.414544792
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test spi_device_csr_mem_rw_with_rand_reset has 6 failures.
3.spi_device_csr_mem_rw_with_rand_reset.26158278931464163713744035593717880192415994332880476919293642848956907850517
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177015573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.177015573
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
8.spi_device_csr_mem_rw_with_rand_reset.60110861219693273154189597321244268846799592450791148609172146902172379556199
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610945895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3610945895
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:33 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 4 more failures.
... and 4 more tests.
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: * has 13 failures:
Test spi_device_flash_and_tpm has 5 failures.
5.spi_device_flash_and_tpm.88684803583707119656296153449931643961727533855153449454704935983443780973942
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/5.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 10195646133 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
UVM_INFO @ 13204152150 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/18
UVM_INFO @ 13490986057 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 3/19
UVM_INFO @ 16346099824 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 4/19
UVM_INFO @ 18831496738 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/18
34.spi_device_flash_and_tpm.10980787014447494413621998561083824735357112574690146395524360264941573270169
Line 264, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/34.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 12934425050 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
UVM_ERROR @ 13368609801 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
UVM_INFO @ 13954987285 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/13
UVM_INFO @ 15979311034 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/13
UVM_INFO @ 18432863996 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/13
... and 3 more failures.
Test spi_device_flash_and_tpm_min_idle has 2 failures.
6.spi_device_flash_and_tpm_min_idle.82881391161658371826376655786813103051229986914042915991885031359303328947703
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 4900331196 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
UVM_INFO @ 5846129196 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 3/18
UVM_INFO @ 5886851196 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 3/12
UVM_INFO @ 6580691196 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 4/12
UVM_INFO @ 7391731196 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 5/12
48.spi_device_flash_and_tpm_min_idle.83822435182760303141838136807679495549769758488007164691597036877822945586169
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 291728194 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
UVM_INFO @ 311408075 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 2/6
UVM_INFO @ 381808985 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 2/15
UVM_INFO @ 648686727 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 3/15
UVM_INFO @ 832558952 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 3/6
Test spi_device_stress_all has 3 failures.
11.spi_device_stress_all.106822882587537433324794731465383273595063243547527230688596862232445469900732
Line 377, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/11.spi_device_stress_all/latest/run.log
UVM_ERROR @ 105455010481 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
UVM_INFO @ 107230413349 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 6/8
UVM_INFO @ 109301414812 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 6/6
UVM_INFO @ 111079526919 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 7/8
UVM_INFO @ 114969846036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
13.spi_device_stress_all.2688323556433631009349728297532189540871339429331585743031457286445697639078
Line 291, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/13.spi_device_stress_all/latest/run.log
UVM_ERROR @ 54421311508 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
UVM_INFO @ 54841887466 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/3
UVM_INFO @ 55960765872 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/5
UVM_INFO @ 56020206421 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/3
UVM_INFO @ 56648528610 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 3/5
... and 1 more failures.
Test spi_device_cfg_cmd has 2 failures.
18.spi_device_cfg_cmd.59148173905450590199264377996756513268308034876935767709417107183087760340164
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/18.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 49727111 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
UVM_INFO @ 50563839 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0x6
UVM_INFO @ 58624999 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 2, test op = 0xb7
UVM_INFO @ 76033063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.spi_device_cfg_cmd.31746258935211701282005631893497388635486059194297466780115377152188526264651
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/19.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 112328245 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
UVM_INFO @ 113768245 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 4, test op = 0xe9
UVM_INFO @ 116848245 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 5, test op = 0x4
UVM_INFO @ 121208245 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 6, test op = 0xb7
UVM_INFO @ 161248245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
Test spi_device_flash_all has 1 failures.
42.spi_device_flash_all.109887514096638259688957818542912234812475859700022031856097906028435872650682
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/42.spi_device_flash_all/latest/run.log
UVM_ERROR @ 627848021 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
UVM_INFO @ 686145416 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/7
UVM_INFO @ 981549022 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/7
UVM_INFO @ 1328916324 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/7
UVM_INFO @ 1649207025 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 6/7
Exit reason: Error: User command failed UVM_ERROR (spi_device_scoreboard.sv:263) [scoreboard] Check failed tpm_read_sw_q.size == * (* [*] vs * [*]) has 2 failures:
Test spi_device_stress_all has 1 failures.
8.spi_device_stress_all.22121795909564608538881404509579337226371382347361827316311386817279740595553
Line 277, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/8.spi_device_stress_all/latest/run.log
UVM_ERROR @ 11278991990 ps: (spi_device_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 11278991990 ps: (uvm_comparer.svh:401) [MISCMP] Miscompare for host_item: lhs = @863947 : rhs = @0
Error-[NOA] Null object access
../src/lowrisc_dv_spi_device_env_0.1/spi_device_scoreboard.sv, 309
Test spi_device_flash_and_tpm has 1 failures.
44.spi_device_flash_and_tpm.81357515665816708202037403717494683055024517667326146277066448148370533361579
Line 263, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/44.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 1629501267 ps: (spi_device_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1629501267 ps: (uvm_comparer.svh:401) [MISCMP] Miscompare for host_item: lhs = @269078 : rhs = @0
Error-[NOA] Null object access
../src/lowrisc_dv_spi_device_env_0.1/spi_device_scoreboard.sv, 309
UVM_ERROR (spi_device_scoreboard.sv:1395) [scoreboard] Check failed rx_word_q.size == * (* [*] vs * [*]) has 2 failures:
15.spi_device_rx_async_fifo_reset.23752508547602708338505972776537205679853046824765418661018986865423743075509
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/15.spi_device_rx_async_fifo_reset/latest/run.log
UVM_ERROR @ 36567445 ps: (spi_device_scoreboard.sv:1395) [uvm_test_top.env.scoreboard] Check failed rx_word_q.size == 0 (2 [0x2] vs 0 [0x0])
UVM_INFO @ 36567445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.spi_device_rx_async_fifo_reset.27494648026565160466310711074503051097114484857810639996667676986087135792462
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/19.spi_device_rx_async_fifo_reset/latest/run.log
UVM_ERROR @ 47917525 ps: (spi_device_scoreboard.sv:1395) [uvm_test_top.env.scoreboard] Check failed rx_word_q.size == 0 (2 [0x2] vs 0 [0x0])
UVM_INFO @ 47917525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:497) scoreboard [scoreboard] flash_status mismatch, backdoor value: *, exp: * has 2 failures:
Test spi_device_flash_all has 1 failures.
17.spi_device_flash_all.94348551337572091469176501906254077263717459282311722551992930671766223837188
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/17.spi_device_flash_all/latest/run.log
UVM_ERROR @ 29230091578 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0xcf3d8, exp: 0xcf3da
UVM_INFO @ 31419817345 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 9/15
UVM_INFO @ 34139054232 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 10/15
UVM_INFO @ 34806291364 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 11/15
UVM_INFO @ 36899899759 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 12/15
Test spi_device_flash_and_tpm has 1 failures.
28.spi_device_flash_and_tpm.33664361994508924184474811265400144200924271167262840106387096102610100322774
Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/28.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 13443204076 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0xe2a424, exp: 0x9ee58
UVM_ERROR @ 13443204076 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0xe2a424, exp: 0x9ee58
UVM_INFO @ 13562424271 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/13
UVM_INFO @ 16222149580 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/13
UVM_INFO @ 17630766267 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/13
UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 2 failures:
22.spi_device_flash_mode.65153749891188549389000780576646330377927297985771947633349081364472185713561
Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/22.spi_device_flash_mode/latest/run.log
UVM_ERROR @ 569608442 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
UVM_ERROR @ 1150248442 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
UVM_INFO @ 1798368442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.spi_device_flash_mode.47067059619641129541372547940662967286899358463830579708190665810174955105292
Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/38.spi_device_flash_mode/latest/run.log
UVM_ERROR @ 538195679 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
UVM_INFO @ 1185435679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_device_base_vseq.sv:413) [spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail has 2 failures:
27.spi_device_stress_all.22485789911511682042422395100546855616176124518414945873147027881126744142624
Line 275, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/27.spi_device_stress_all/latest/run.log
UVM_FATAL @ 1069802862756 ps: (spi_device_base_vseq.sv:413) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail
UVM_INFO @ 1069802862756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.spi_device_stress_all.67827484798274421068691036133726454918247080530880102459800219903502033627278
Line 339, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/38.spi_device_stress_all/latest/run.log
UVM_FATAL @ 16600545003 ps: (spi_device_base_vseq.sv:413) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail
UVM_INFO @ 16600545003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.status.txf_full reset value: * has 2 failures:
29.spi_device_intr.115646306065837164835411065875345783325442791972005593291396065318651481030300
Line 283, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/29.spi_device_intr/latest/run.log
UVM_ERROR @ 16747612746 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.txf_full reset value: 0x0
UVM_INFO @ 16834972746 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]
Testing RxFifoFull
UVM_INFO @ 20078492746 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]
Testing RxFifoGeLevel
37.spi_device_intr.86443341713794504696879006223805069249636056002095100875273810429400369504825
Line 281, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/37.spi_device_intr/latest/run.log
UVM_ERROR @ 3906860194 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.txf_full reset value: 0x0
UVM_INFO @ 3925892053 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]
Testing RxFwModeErr
UVM_INFO @ 3926037891 ps: (spi_device_intr_vseq.sv:43) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq]
Testing RxFifoFull
UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:
8.spi_device_mailbox.5174328024973172593451032975207273334920560259860785505459388025229761911150
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/8.spi_device_mailbox/latest/run.log
UVM_ERROR @ 337407607 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x94d570) != exp '{'{other_status:'h1fb390, wel:'h0, busy:'h0}, '{other_status:'hdcce6, wel:'h0, busy:'h0}}
UVM_INFO @ 458106515 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_mailbox_vseq] running iteration 7, test op = 0x15
UVM_INFO @ 504691983 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_mailbox_vseq] running iteration 8, test op = 0x5
UVM_INFO @ 518879883 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_mailbox_vseq] running iteration 9, test op = 0x5
UVM_INFO @ 533074259 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_mailbox_vseq] running iteration 10, test op = 0x15
Job spi_device-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
8.spi_device_tl_errors.65245210273112346676965617450589547108629109561648940418425429669143244460794
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/8.spi_device_tl_errors/latest/run.log
Job ID: smart:365238a5-87d6-4d4b-9ba7-b874546422d3
Job spi_device-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
9.spi_device_stress_all.37589751254964460204824713148437739062129640353607952875987357852095088368873
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/9.spi_device_stress_all/latest/run.log
Job ID: smart:bcaa8c32-d57a-40ee-b6aa-4e6e75938379
UVM_ERROR (spi_device_pass_base_vseq.sv:641) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:
11.spi_device_flash_all.111787278027960962001058938782389613986753723834613025858435694569842536385387
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/11.spi_device_flash_all/latest/run.log
UVM_ERROR @ 3752703053 ps: (spi_device_pass_base_vseq.sv:641) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
UVM_INFO @ 3782243244 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 13/14
UVM_INFO @ 4182154135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:365) [spi_device_intr_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 1 failures:
40.spi_device_stress_all.87493120195133468873913169220562007636642355353266066637930948065799485354355
Line 271, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/40.spi_device_stress_all/latest/run.log
UVM_ERROR @ 111907338192 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 111907799730 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
UVM_ERROR @ 111914876646 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
UVM_ERROR @ 111917184336 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0
UVM_ERROR @ 111917953566 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.rxf_full reset value: 0x0
UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 1 failures:
41.spi_device_flash_mode.41771214060374261656658147861044143959584196438230324594290615448182168127348
Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/41.spi_device_flash_mode/latest/run.log
UVM_ERROR @ 3113521399 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
UVM_ERROR @ 3379721399 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
UVM_INFO @ 3507311399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 1 failures:
42.spi_device_flash_and_tpm_min_idle.109365562224211840919186216333930252640030154648519717691628683972182477015083
Line 277, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 39627841572 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
UVM_INFO @ 39928651572 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 14/19
UVM_INFO @ 42143467572 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 16/18
UVM_INFO @ 43484161572 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 15/19
UVM_INFO @ 43632493572 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 17/18
UVM_ERROR (spi_device_scoreboard.sv:1257) [scoreboard] Check failed data_act == data_exp (* [*] vs * [*]) Compare SPI TX data has 1 failures:
45.spi_device_stress_all.72653428624120186094570991916020306503205137657608471653928068435321501550164
Line 281, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/45.spi_device_stress_all/latest/run.log
UVM_ERROR @ 447038524221 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (2043170178 [0x79c84d82] vs 3469720505 [0xcecfbbb9]) Compare SPI TX data
UVM_ERROR @ 447234661221 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (2862254205 [0xaa9a887d] vs 2188490588 [0x8271b75c]) Compare SPI TX data
UVM_ERROR @ 447249721221 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (4224786891 [0xfbd121cb] vs 561110657 [0x2171de81]) Compare SPI TX data
UVM_ERROR @ 447262890221 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (381806822 [0x16c1e8e6] vs 110001888 [0x68e7ee0]) Compare SPI TX data
UVM_ERROR @ 447278625221 ps: (spi_device_scoreboard.sv:1257) [uvm_test_top.env.scoreboard] Check failed data_act == data_exp (3993256182 [0xee0440f6] vs 3160542763 [0xbc620e2b]) Compare SPI TX data