SPI_DEVICE Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: 5f48fbc0e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_smoke 0 50 0.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.490s 46.215us 5 5 100.00
V1 csr_rw spi_device_csr_rw 3.160s 487.864us 20 20 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 36.480s 2.614ms 5 5 100.00
V1 csr_aliasing spi_device_csr_aliasing 30.120s 2.941ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.270s 43.626us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 3.160s 487.864us 20 20 100.00
spi_device_csr_aliasing 30.120s 2.941ms 5 5 100.00
V1 mem_walk spi_device_mem_walk 12.490s 2.643ms 5 5 100.00
V1 mem_partial_access spi_device_mem_partial_access 6.620s 772.434us 5 5 100.00
V1 TOTAL 65 115 56.52
V2 base_random_seq spi_device_txrx 0 50 0.00
V2 fifo_full spi_device_fifo_full 0 50 0.00
V2 fifo_underflow_overflow spi_device_fifo_underflow_overflow 0 50 0.00
V2 dummy_sck_and_dummy_csb spi_device_dummy_item_extra_dly 0 50 0.00
V2 extra_delay_on_spi spi_device_dummy_item_extra_dly 0 50 0.00
V2 tx_async_fifo_reset spi_device_tx_async_fifo_reset 0 50 0.00
V2 rx_async_fifo_reset spi_device_rx_async_fifo_reset 0 50 0.00
V2 interrupts spi_device_intr 0 50 0.00
V2 abort spi_device_abort 0 50 0.00
V2 byte_transfer_on_spi spi_device_byte_transfer 0 50 0.00
V2 rx_timeout spi_device_rx_timeout 0 50 0.00
V2 bit_transfer_on_spi spi_device_bit_transfer 0 50 0.00
V2 extreme_fifo_setting spi_device_extreme_fifo_size 0 50 0.00
V2 perf spi_device_perf 0 50 0.00
V2 csb_read spi_device_csb_read 0 50 0.00
V2 mem_parity spi_device_mem_parity 0 20 0.00
V2 mem_cfg spi_device_ram_cfg 0 20 0.00
V2 tpm_read spi_device_tpm_rw 0 50 0.00
V2 tpm_write spi_device_tpm_rw 0 50 0.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 0 50 0.00
spi_device_tpm_sts_read 0 50 0.00
V2 tpm_fully_random_case spi_device_tpm_all 0 50 0.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 0 50 0.00
spi_device_flash_all 0 50 0.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 0 50 0.00
spi_device_flash_all 0 50 0.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 0 50 0.00
spi_device_flash_all 0 50 0.00
V2 cmd_info_slots spi_device_flash_all 0 50 0.00
V2 cmd_read_status spi_device_intercept 0 50 0.00
spi_device_flash_all 0 50 0.00
V2 cmd_read_jedec spi_device_intercept 0 50 0.00
spi_device_flash_all 0 50 0.00
V2 cmd_read_sfdp spi_device_intercept 0 50 0.00
spi_device_flash_all 0 50 0.00
V2 cmd_fast_read spi_device_intercept 0 50 0.00
spi_device_flash_all 0 50 0.00
V2 flash_cmd_upload spi_device_upload 0 50 0.00
V2 mailbox_command spi_device_mailbox 0 50 0.00
V2 mailbox_cross_outside_command spi_device_mailbox 0 50 0.00
V2 mailbox_cross_inside_command spi_device_mailbox 0 50 0.00
V2 cmd_read_buffer spi_device_flash_mode 0 50 0.00
spi_device_read_buffer_direct 0 50 0.00
V2 cmd_dummy_cycle spi_device_mailbox 0 50 0.00
spi_device_flash_all 0 50 0.00
V2 quad_spi spi_device_flash_all 0 50 0.00
V2 dual_spi spi_device_flash_all 0 50 0.00
V2 4b_3b_feature spi_device_cfg_cmd 0 50 0.00
V2 write_enable_disable spi_device_cfg_cmd 0 50 0.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 0 50 0.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 0 50 0.00
V2 stress_all spi_device_stress_all 0 50 0.00
V2 alert_test spi_device_alert_test 0 50 0.00
V2 intr_test spi_device_intr_test 0.810s 49.014us 50 50 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 5.440s 977.423us 20 20 100.00
V2 tl_d_illegal_access spi_device_tl_errors 5.440s 977.423us 20 20 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.490s 46.215us 5 5 100.00
spi_device_csr_rw 3.160s 487.864us 20 20 100.00
spi_device_csr_aliasing 30.120s 2.941ms 5 5 100.00
spi_device_same_csr_outstanding 4.340s 184.021us 20 20 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.490s 46.215us 5 5 100.00
spi_device_csr_rw 3.160s 487.864us 20 20 100.00
spi_device_csr_aliasing 30.120s 2.941ms 5 5 100.00
spi_device_same_csr_outstanding 4.340s 184.021us 20 20 100.00
V2 TOTAL 90 1680 5.36
V2S tl_intg_err spi_device_sec_cm 0 5 0.00
spi_device_tl_intg_err 23.250s 22.664ms 20 20 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 23.250s 22.664ms 20 20 100.00
V2S TOTAL 20 25 80.00
V3 stress_all_with_rand_reset spi_device_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 175 1820 9.62

Testplan Progress

Items Total Written Passing Progress
V1 8 8 7 87.50
V2 36 36 3 8.33
V2S 2 2 1 50.00
V3 1 0 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
60.02 71.17 76.17 75.34 0.00 77.00 100.00 20.49

Failure Buckets

Past Results