SPI_DEVICE Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: `4d88b9516c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke	1.450s	1.060ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.460s	49.714us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.250s	531.823us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.370s	1.130ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.510s	1.902ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.460s	43.834us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.250s	531.823us	20	20	100.00
		spi_device_csr_aliasing	10.510s	1.902ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	15.970s	3.908ms	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	7.830s	74.464us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	base_random_seq	spi_device_txrx	43.209m	310.151ms	50	50	100.00
V2	fifo_full	spi_device_fifo_full	51.273m	51.886ms	49	50	98.00
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	26.328m	391.914ms	50	50	100.00
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	46.078m	100.465ms	50	50	100.00
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	46.078m	100.465ms	50	50	100.00
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	0.820s	53.811us	50	50	100.00
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	1.040s	35.716us	50	50	100.00
V2	interrupts	spi_device_intr	2.190m	35.113ms	50	50	100.00
V2	abort	spi_device_abort	0.800s	14.906us	50	50	100.00
V2	byte_transfer_on_spi	spi_device_byte_transfer	4.610s	329.851us	50	50	100.00
V2	rx_timeout	spi_device_rx_timeout	7.480s	972.397us	50	50	100.00
V2	bit_transfer_on_spi	spi_device_bit_transfer	4.240s	3.187ms	50	50	100.00
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	1.070h	77.196ms	50	50	100.00
V2	perf	spi_device_perf	48.021m	458.339ms	49	50	98.00
V2	csb_read	spi_device_csb_read	0.880s	33.264us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.150s	119.317us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.860s	15.751us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	15.020s	2.436ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	15.020s	2.436ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	31.020s	55.275ms	50	50	100.00
		spi_device_tpm_sts_read	1.150s	1.497ms	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.460m	55.690ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.128m	134.191ms	50	50	100.00
		spi_device_flash_all	7.396m	331.513ms	45	50	90.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	50.520s	147.315ms	50	50	100.00
		spi_device_flash_all	7.396m	331.513ms	45	50	90.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	50.520s	147.315ms	50	50	100.00
		spi_device_flash_all	7.396m	331.513ms	45	50	90.00
V2	cmd_info_slots	spi_device_flash_all	7.396m	331.513ms	45	50	90.00
V2	cmd_read_status	spi_device_intercept	15.360s	26.994ms	50	50	100.00
		spi_device_flash_all	7.396m	331.513ms	45	50	90.00
V2	cmd_read_jedec	spi_device_intercept	15.360s	26.994ms	50	50	100.00
		spi_device_flash_all	7.396m	331.513ms	45	50	90.00
V2	cmd_read_sfdp	spi_device_intercept	15.360s	26.994ms	50	50	100.00
		spi_device_flash_all	7.396m	331.513ms	45	50	90.00
V2	cmd_fast_read	spi_device_intercept	15.360s	26.994ms	50	50	100.00
		spi_device_flash_all	7.396m	331.513ms	45	50	90.00
V2	flash_cmd_upload	spi_device_upload	56.740s	114.617ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	52.920s	94.911ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	52.920s	94.911ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	52.920s	94.911ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.626m	84.437ms	48	50	96.00
		spi_device_read_buffer_direct	7.750s	3.694ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	52.920s	94.911ms	50	50	100.00
		spi_device_flash_all	7.396m	331.513ms	45	50	90.00
V2	quad_spi	spi_device_flash_all	7.396m	331.513ms	45	50	90.00
V2	dual_spi	spi_device_flash_all	7.396m	331.513ms	45	50	90.00
V2	4b_3b_feature	spi_device_cfg_cmd	13.820s	3.503ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	13.820s	3.503ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.295m	99.625ms	47	50	94.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.308m	69.920ms	48	50	96.00
V2	stress_all	spi_device_stress_all	2.037h	225.664ms	40	50	80.00
V2	alert_test	spi_device_alert_test	0.820s	42.014us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	31.974us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.000s	269.411us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.000s	269.411us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.460s	49.714us	5	5	100.00
		spi_device_csr_rw	3.250s	531.823us	20	20	100.00
		spi_device_csr_aliasing	10.510s	1.902ms	5	5	100.00
		spi_device_same_csr_outstanding	4.490s	359.881us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.460s	49.714us	5	5	100.00
		spi_device_csr_rw	3.250s	531.823us	20	20	100.00
		spi_device_csr_aliasing	10.510s	1.902ms	5	5	100.00
		spi_device_same_csr_outstanding	4.490s	359.881us	20	20	100.00
V2		TOTAL			1656	1680	98.57
V2S	tl_intg_err	spi_device_sec_cm	1.240s	541.990us	5	5	100.00
		spi_device_tl_intg_err	25.860s	3.474ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.860s	3.474ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1796	1820	98.68

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	36	36	29	80.56
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.10	99.01	96.32	98.63	92.06	98.05	95.86	99.76

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: * has 7 failures:

Test spi_device_flash_and_tpm has 2 failures.

2.spi_device_flash_and_tpm.31296744867131691163855345599163331568996980143401259933887244973807339049157
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/2.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 13836199866 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 13960271344 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/20
  UVM_INFO @ 15110543394 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 13/15
  UVM_INFO @ 15407553967 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/20
  UVM_INFO @ 16046300880 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 14/15

20.spi_device_flash_and_tpm.101446457251544344341015641912527397851165673435358791673946501460358341468029
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/20.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 6686180608 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 6977609608 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 3/9
  UVM_INFO @ 9073536733 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 4/9
  UVM_INFO @ 11578726233 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 5/9
  UVM_INFO @ 13269305608 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 6/9

Test spi_device_flash_all has 2 failures.

10.spi_device_flash_all.42473084460792748296071622733610309317467290446327811146954351398858994977343
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/10.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 11255847552 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 11294597862 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 12/18
  UVM_INFO @ 13217863248 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 13/18
  UVM_INFO @ 14110342610 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 14/18
  UVM_INFO @ 14988784738 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 15/18

48.spi_device_flash_all.26824543926618771165235320255737037142764767014817424866371457391046335709376
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/48.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 2417311594 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 2527901513 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 13/14
  UVM_INFO @ 2882795079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_stress_all has 3 failures.

24.spi_device_stress_all.55345697099850269543315448403018406309981431957657580554671801305049413619938
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/24.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 17887483591 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 19522883591 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 22561860591 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 5/10
  UVM_INFO @ 23565463591 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/6
  UVM_INFO @ 26482223591 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 6/10

25.spi_device_stress_all.39641299084766927437200889528247739647204187390598303508424637268743721787898
Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/25.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 26256883963 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 28239125213 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/17
  UVM_INFO @ 33386268463 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/17
  UVM_INFO @ 35188508963 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/17
  UVM_INFO @ 37634446963 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/17

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:365) [spi_device_intr_vseq] Check failed act_pins == exp_pins (* [*] vs * [*]) has 2 failures:

Test spi_device_stress_all has 2 failures.

4.spi_device_stress_all.81966936220098646593042519062078011898900238807109564759557343311742273928994
Line 264, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/4.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 8010521252 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 8010621252 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 8015911252 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
  UVM_ERROR @ 8018601252 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 8018821252 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.rxf_full reset value: 0x0

32.spi_device_stress_all.30445299462869014923876866584508942847989726885821768128374048827655087989056
Line 295, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/32.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 462946363137 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 462946505994 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 462956172651 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
  UVM_ERROR @ 462959601886 ps: (cip_base_vseq.sv:365) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed act_pins == exp_pins (0 [0x0] vs 16 [0x10])
  UVM_ERROR @ 462960220266 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0

UVM_FATAL (spi_device_base_vseq.sv:413) [spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail has 2 failures:
- Test spi_device_stress_all has 2 failures.
  - 14.spi_device_stress_all.51553134534534975117906371982913435930370487437998442505269692322749024018832
    Line 268, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/14.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 20119406620 ps: (spi_device_base_vseq.sv:413) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail
  UVM_INFO @ 20119406620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.spi_device_stress_all.102301312811574282063063912099492745734279271228304190232795170810965938137240
    Line 286, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/31.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 89864801126 ps: (spi_device_base_vseq.sv:413) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail
  UVM_INFO @ 89864801126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job spi_device-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test spi_device_perf has 1 failures.
  - 28.spi_device_perf.103515452308636875992551969170093946452793067277361626779479998120709281393614
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/28.spi_device_perf/latest/run.log
```
  Job ID: smart:8e2cdfe9-e4c4-40ef-8646-531f0ebb5bff
```
- Test spi_device_fifo_full has 1 failures.
  - 36.spi_device_fifo_full.96747099360093734706146846532010224014620527518213415268478176923752056697939
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/36.spi_device_fifo_full/latest/run.log
```
  Job ID: smart:5b47b539-909c-4d9e-bda8-aa82887d8dbf
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_all has 1 failures.
  - 4.spi_device_flash_all.3252321066933592584681508921883087460009984087316253502887078834956728718129
    Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/4.spi_device_flash_all/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

8.spi_device_flash_and_tpm.1039136497183653255631670426025884462815732810156684724734462926598696388748
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/8.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 2734607754 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 2765753784 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/11
  UVM_INFO @ 3708549234 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/11
  UVM_INFO @ 3737829474 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/4
  UVM_INFO @ 5989938914 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 3/4

UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 1 failures:

Test spi_device_stress_all has 1 failures.

15.spi_device_stress_all.54846757623076274132528589707056741917279386755152782928697829812342155123856
Line 323, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/15.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 159601207913 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_ERROR @ 159970326214 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xb [1011] vs 0xed [11101101]) addr 0xc9f6987b read out mismatch
  UVM_ERROR @ 159970326214 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x77 [1110111] vs 0x84 [10000100]) addr 0xc9f6987c read out mismatch
  UVM_ERROR @ 159970326214 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x32 [110010] vs 0x87 [10000111]) addr 0xc9f6987d read out mismatch
  UVM_ERROR @ 159970326214 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xaa [10101010] vs 0xd5 [11010101]) addr 0xc9f6987e read out mismatch

UVM_ERROR (spi_device_scoreboard.sv:436) scoreboard [scoreboard] Compare TPM reg failed, offset: *, act: *, exp: '{*} has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

21.spi_device_flash_and_tpm_min_idle.25863565442261384821909523868988038855059737031541680901301996896156866125820
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @   9523511 ps: (spi_device_scoreboard.sv:436) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare TPM reg failed, offset: 0, act: 0x59b3ff8, exp: '{'hffffff31}
  UVM_FATAL @  53229761 ps: (spi_device_scoreboard.sv:1165) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @  53229761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_flash_all has 1 failures.

30.spi_device_flash_all.110991579315170082286096808667650326076814702881756261956105590241624884939288
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/30.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 962514946 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3c5682) != exp '{'{other_status:'hf15a0, wel:'h0, busy:'h0}}
  UVM_INFO @ 1152534274 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 2/5
  UVM_INFO @ 1312837771 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/5
  UVM_INFO @ 1766117502 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/5
  UVM_INFO @ 2292619848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_stress_all has 1 failures.

30.spi_device_stress_all.32461592202824040479667243459697488444133657684457122560866144119190402262803
Line 320, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/30.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 106482368342 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xc58f66) != exp '{'{other_status:'h114a1f, wel:'h0, busy:'h0}, '{other_status:'h252c5b, wel:'h1, busy:'h0}}
  UVM_INFO @ 107091337765 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/8
  UVM_INFO @ 115579535285 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/13
  UVM_INFO @ 119854175223 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 3/8
  UVM_INFO @ 128001648695 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 4/8

UVM_ERROR (spi_device_scoreboard.sv:497) scoreboard [scoreboard] flash_status mismatch, backdoor value: *, exp: * has 1 failures:

Test spi_device_flash_all has 1 failures.

34.spi_device_flash_all.37397740434530162266485411163798487368738558920505731034776551985586704003879
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/34.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 54823386617 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0x509794, exp: 0xd5da0c
  UVM_ERROR @ 54823386617 ps: (spi_device_scoreboard.sv:497) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0x509794, exp: 0xd5da0c
  UVM_INFO @ 59339369744 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 8/10
  UVM_INFO @ 63622910188 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 9/10
  UVM_INFO @ 69816734464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_FATAL (spi_device_scoreboard.sv:890) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 36.spi_device_flash_mode.54708489779884134511858664151829989664004432751761177725357590940836072026919
    Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/36.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 77796797190 ps: (spi_device_scoreboard.sv:890) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 77796797190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_pass_base_vseq.sv:641) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

39.spi_device_flash_and_tpm_min_idle.7585093684278079678163747798598481413973554019447024178881822241913718756535
Line 271, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 28096765719 ps: (spi_device_pass_base_vseq.sv:641) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 28877228069 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 13/18
  UVM_INFO @ 29460716630 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 11/17
  UVM_INFO @ 31347980049 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 12/17
  UVM_INFO @ 31620119134 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 14/18

UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 47.spi_device_flash_mode.1792797403945333750416411316976586471659306654304210969114941997388225777100
    Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/47.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 883412901 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 946952901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (* [*] vs * [*]) get_sram_space_bytes:: has 1 failures:

Test spi_device_stress_all has 1 failures.

47.spi_device_stress_all.88120689106868108505881188855056867484795537119192028846561856009591284488701
Line 317, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/47.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 1647234265026 ps: (spi_device_env_pkg.sv:177) [read_tx_avail_bytes] Check failed rptr >= wptr (4 [0x4] vs 44 [0x2c]) get_sram_space_bytes::
  UVM_ERROR @ 1647238965026 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x2f
  UVM_ERROR @ 1647238965026 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x2e
  UVM_ERROR @ 1647238965026 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x2d
  UVM_ERROR @ 1647238965026 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x2c