SPI_DEVICE Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: `796f9fb805`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke	1.370s	42.421us	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.520s	95.546us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.940s	101.592us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	30.810s	3.981ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	25.890s	699.957us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.300s	120.162us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.940s	101.592us	20	20	100.00
		spi_device_csr_aliasing	25.890s	699.957us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	14.780s	719.086us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	4.890s	731.874us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	base_random_seq	spi_device_txrx	40.387m	200.236ms	50	50	100.00
V2	fifo_full	spi_device_fifo_full	59.369m	64.926ms	49	50	98.00
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow	34.497m	408.618ms	50	50	100.00
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly	23.584m	70.246ms	48	50	96.00
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly	23.584m	70.246ms	48	50	96.00
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset	0.870s	83.350us	50	50	100.00
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset	1.020s	144.770us	48	50	96.00
V2	interrupts	spi_device_intr	2.655m	148.909ms	50	50	100.00
V2	abort	spi_device_abort	0.830s	25.038us	50	50	100.00
V2	byte_transfer_on_spi	spi_device_byte_transfer	4.350s	673.201us	50	50	100.00
V2	rx_timeout	spi_device_rx_timeout	7.830s	894.896us	49	50	98.00
V2	bit_transfer_on_spi	spi_device_bit_transfer	4.070s	452.738us	49	50	98.00
V2	extreme_fifo_setting	spi_device_extreme_fifo_size	1.117h	70.469ms	50	50	100.00
V2	perf	spi_device_perf	51.059m	94.610ms	48	50	96.00
V2	csb_read	spi_device_csb_read	0.870s	69.674us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.190s	14.598us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.820s	23.624us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	11.490s	611.391us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.490s	611.391us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	41.080s	55.129ms	50	50	100.00
		spi_device_tpm_sts_read	1.260s	151.945us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.399m	153.359ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	48.590s	66.714ms	50	50	100.00
		spi_device_flash_all	11.494m	539.741ms	46	50	92.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	50.200s	75.049ms	50	50	100.00
		spi_device_flash_all	11.494m	539.741ms	46	50	92.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	50.200s	75.049ms	50	50	100.00
		spi_device_flash_all	11.494m	539.741ms	46	50	92.00
V2	cmd_info_slots	spi_device_flash_all	11.494m	539.741ms	46	50	92.00
V2	cmd_read_status	spi_device_intercept	18.090s	20.156ms	50	50	100.00
		spi_device_flash_all	11.494m	539.741ms	46	50	92.00
V2	cmd_read_jedec	spi_device_intercept	18.090s	20.156ms	50	50	100.00
		spi_device_flash_all	11.494m	539.741ms	46	50	92.00
V2	cmd_read_sfdp	spi_device_intercept	18.090s	20.156ms	50	50	100.00
		spi_device_flash_all	11.494m	539.741ms	46	50	92.00
V2	cmd_fast_read	spi_device_intercept	18.090s	20.156ms	50	50	100.00
		spi_device_flash_all	11.494m	539.741ms	46	50	92.00
V2	flash_cmd_upload	spi_device_upload	41.030s	108.175ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	49.500s	16.169ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	49.500s	16.169ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	49.500s	16.169ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.358m	12.276ms	47	50	94.00
		spi_device_read_buffer_direct	7.830s	8.734ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	49.500s	16.169ms	50	50	100.00
		spi_device_flash_all	11.494m	539.741ms	46	50	92.00
V2	quad_spi	spi_device_flash_all	11.494m	539.741ms	46	50	92.00
V2	dual_spi	spi_device_flash_all	11.494m	539.741ms	46	50	92.00
V2	4b_3b_feature	spi_device_cfg_cmd	15.540s	19.337ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	15.540s	19.337ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	15.318m	1.105s	46	50	92.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	16.950m	267.956ms	44	50	88.00
V2	stress_all	spi_device_stress_all	1.723h	153.260ms	38	50	76.00
V2	alert_test	spi_device_alert_test	0.790s	22.887us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.870s	14.201us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.750s	822.161us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.750s	822.161us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.520s	95.546us	5	5	100.00
		spi_device_csr_rw	2.940s	101.592us	20	20	100.00
		spi_device_csr_aliasing	25.890s	699.957us	5	5	100.00
		spi_device_same_csr_outstanding	4.960s	924.445us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.520s	95.546us	5	5	100.00
		spi_device_csr_rw	2.940s	101.592us	20	20	100.00
		spi_device_csr_aliasing	25.890s	699.957us	5	5	100.00
		spi_device_same_csr_outstanding	4.960s	924.445us	20	20	100.00
V2		TOTAL			1642	1680	97.74
V2S	tl_intg_err	spi_device_sec_cm	1.250s	110.736us	5	5	100.00
		spi_device_tl_intg_err	25.300s	3.446ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.300s	3.446ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1782	1820	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	36	36	25	69.44
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.10	99.01	96.33	98.63	92.06	98.05	95.86	99.76

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: * has 14 failures:

Test spi_device_flash_all has 3 failures.

6.spi_device_flash_all.54372653438572543027943779824789989494951529991360518340600014383671245770676
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/6.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 389672592 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 655830882 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 1/10
  UVM_ERROR @ 1171752592 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 1576414506 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 2/10
  UVM_INFO @ 2221387842 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/10

26.spi_device_flash_all.32658755391035623571027385494375557262056369749472522873659308202837733470392
Line 258, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/26.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 7869078968 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 7931003531 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 10/15
  UVM_INFO @ 9030338258 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 11/15
  UVM_INFO @ 10183462790 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 12/15
  UVM_INFO @ 10791737712 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 13/15

... and 1 more failures.

Test spi_device_stress_all has 6 failures.

15.spi_device_stress_all.21166001255472006307762968326146934060960761099500701082421888358070383784558
Line 287, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/15.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 289728872321 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 289751236969 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/9
  UVM_INFO @ 289846549951 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/15
  UVM_INFO @ 290189011497 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/15
  UVM_INFO @ 291005933533 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/15

19.spi_device_stress_all.93588518043914404598469506250316858551555261548178463769639420105065933153435
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/19.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 451316540 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 480956312 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/11
  UVM_INFO @ 481010567 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/13
  UVM_INFO @ 717214016 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/11
  UVM_INFO @ 798638678 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 3/13

... and 4 more failures.

Test spi_device_flash_and_tpm has 3 failures.

17.spi_device_flash_and_tpm.106477173783362383917414720967780192722802759012413761233561980727538810002112
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/17.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 10175491440 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 10702939300 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/16
  UVM_INFO @ 11765879163 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/16
  UVM_INFO @ 14113206319 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/16
  UVM_INFO @ 14751774969 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/16

19.spi_device_flash_and_tpm.72975990835499264565083170308959502222386069109613266848237756229048354247208
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/19.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 196977146829 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 201843212985 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 12/15
  UVM_INFO @ 209502436266 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 10/11
  UVM_INFO @ 210531296993 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 13/15
  UVM_INFO @ 219516853495 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 11/11

... and 1 more failures.

Test spi_device_flash_and_tpm_min_idle has 2 failures.

33.spi_device_flash_and_tpm_min_idle.83223326978137249557748718464825943617870778104044289053950897292910403829835
Line 265, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 8468234239 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 8512472756 ps: (uvm_comparer.svh:351) [MISCMP] Miscompare for host_item.payload_q:
  UVM_INFO @ 8512472756 ps: (uvm_comparer.svh:382) [MISCMP] 1 Miscompare(s) for object host_item@546870 vs. host_item@546878
  UVM_ERROR @ 8512472756 ps: (spi_device_scoreboard.sv:838) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare failed, downstream item:
  -------------------------------------------------------------

37.spi_device_flash_and_tpm_min_idle.21509242348349838877083945270185248987932822262824949956196873131018719991307
Line 265, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 3424580404 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 3492443966 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 8/16
  UVM_INFO @ 4014136598 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 9/16
  UVM_INFO @ 4290026640 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 10/16
  UVM_INFO @ 4560599184 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 11/16

Job spi_device-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test spi_device_dummy_item_extra_dly has 2 failures.
  - 3.spi_device_dummy_item_extra_dly.61791146164918658723145718538545282881717360021686044443447045688148636479413
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_dummy_item_extra_dly/latest/run.log
```
  Job ID: smart:6824e41b-d90d-4830-bc9b-d0c4717f7abf
```
  - 34.spi_device_dummy_item_extra_dly.58565058324586647073440895303897828927284473880891464078079644631725232644743
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/34.spi_device_dummy_item_extra_dly/latest/run.log
```
  Job ID: smart:281ea844-3173-4400-a527-a72e050e6efa
```
- Test spi_device_fifo_full has 1 failures.
  - 10.spi_device_fifo_full.101950003300084439867811833356565403936794576395980865711435217139093029948484
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/10.spi_device_fifo_full/latest/run.log
```
  Job ID: smart:0e90337d-2b43-425a-8fda-1f5138631778
```
- Test spi_device_perf has 2 failures.
  - 36.spi_device_perf.68503702269093635438733483463419281286550383838826412797064212160994206507519
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/36.spi_device_perf/latest/run.log
```
  Job ID: smart:89640d9d-56af-4524-9854-acce70bbd94c
```
  - 49.spi_device_perf.57352368878454289165406263019439040690142254000712167046931116500493760878657
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/49.spi_device_perf/latest/run.log
```
  Job ID: smart:6c79a2d9-eb85-43a1-8b57-8ac13b4291b6
```
UVM_FATAL (spi_device_base_vseq.sv:413) [spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail has 3 failures:
- Test spi_device_stress_all has 3 failures.
  - 26.spi_device_stress_all.48920763439636058005512794187269503341279949206463171787300558087758658052683
    Line 337, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/26.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 85554001786 ps: (spi_device_base_vseq.sv:413) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail
  UVM_INFO @ 85554001786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.spi_device_stress_all.77558632788929816036771680621781170513631204612535676046019099139040648168231
    Line 337, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/31.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 12163890791 ps: (spi_device_base_vseq.sv:413) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] wait_for_rx_avail_bytes::SramDataAvail
  UVM_INFO @ 12163890791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 2 failures:
- Test spi_device_flash_mode has 2 failures.
  - 0.spi_device_flash_mode.82500197112106281570147419624783990121522954337741766185339893781602483502452
    Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 1796011296 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 3665026208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.spi_device_flash_mode.76452003156704689450384654803543463224427701871083859639932443138487881942419
    Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/20.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 6057571691 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 17619502349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (spi_device_scoreboard.sv:1395) [scoreboard] Check failed rx_word_q.size == * (* [*] vs * [*]) has 2 failures:
- Test spi_device_rx_async_fifo_reset has 2 failures.
  - 1.spi_device_rx_async_fifo_reset.98116455212616635890594814524387432951348869270023762056201645456443311706604
    Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_rx_async_fifo_reset/latest/run.log
```
  UVM_ERROR @  24089014 ps: (spi_device_scoreboard.sv:1395) [uvm_test_top.env.scoreboard] Check failed rx_word_q.size == 0 (2 [0x2] vs 0 [0x0])
  UVM_INFO @  24089014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.spi_device_rx_async_fifo_reset.85415312777727449253564197520883143024617049615526084410849575321641124576994
    Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_rx_async_fifo_reset/latest/run.log
```
  UVM_ERROR @ 346893160 ps: (spi_device_scoreboard.sv:1395) [uvm_test_top.env.scoreboard] Check failed rx_word_q.size == 0 (2 [0x2] vs 0 [0x0])
  UVM_INFO @ 346893160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed Job returned non-zero exit code has 2 failures:

Test spi_device_bit_transfer has 1 failures.

26.spi_device_bit_transfer.20096756572244702762863072242775802645582912999827896646176361124443653920909
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/26.spi_device_bit_transfer/latest/run.log

  [make]: simulate
  cd /workspace/26.spi_device_bit_transfer/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010030733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_bit_transfer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_bit_transfer.1010030733
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan 21 20:02 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

Test spi_device_flash_and_tpm_min_idle has 1 failures.

26.spi_device_flash_and_tpm_min_idle.20743719009308434772195336800582236180101730767868767058989241249817456007843
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest/run.log

  [make]: simulate
  cd /workspace/26.spi_device_flash_and_tpm_min_idle/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606853795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.606853795
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Jan 21 20:02 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.intr_state reset value: * has 1 failures:

Test spi_device_stress_all has 1 failures.

3.spi_device_stress_all.30404481169294874811462321666586094072744373267700931401699785485512077981138
Line 307, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 86159702206 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 86161823416 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.status.rxf_empty reset value: 0x1
  UVM_ERROR @ 86162702203 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 16 [0x10]) Regname: spi_device_reg_block.intr_state reset value: 0x0
  UVM_ERROR @ 86163096142 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.status.rxf_full reset value: 0x0
  UVM_ERROR @ 86478328150 ps: (spi_device_base_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.spi_device_intr_vseq] Check failed rx_avail_bytes == 0 (4 [0x4] vs 0 [0x0])

UVM_ERROR (spi_device_scoreboard.sv:1085) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

7.spi_device_flash_and_tpm_min_idle.100492666197872593008027497717707960238571586711817150901599481311015198047156
Line 265, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 17152433726 ps: (spi_device_scoreboard.sv:1085) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 18370778293 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 7/11
  UVM_INFO @ 18425512793 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 11/12
  UVM_INFO @ 20549525537 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 12/12
  UVM_INFO @ 22173130343 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 8/11

UVM_ERROR (spi_device_scoreboard.sv:436) scoreboard [scoreboard] Compare TPM reg failed, offset: *, act: *, exp: '{*, *} has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

18.spi_device_flash_and_tpm_min_idle.34863246400301940854448052059397832519524419455187135476766566648039427949983
Line 277, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 4351965364 ps: (spi_device_scoreboard.sv:436) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare TPM reg failed, offset: 0, act: 0xdf1f3470, exp: '{'h53f953ad, 'h11188f9a}
  UVM_FATAL @ 4359080395 ps: (spi_device_scoreboard.sv:1165) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4359080395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_scoreboard.sv:1214) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) CSR upload_status* compare mismatch act * != exp *` has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

20.spi_device_flash_and_tpm.17353036324736250067265291508629587133583103556822097245744748256626632305384
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/20.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 2624796255 ps: (spi_device_scoreboard.sv:1214) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (129 [0x81] vs 128 [0x80]) CSR upload_status2 compare mismatch act 0x81 != exp 0x80
  UVM_ERROR @ 2626212933 ps: (spi_device_scoreboard.sv:1137) [uvm_test_top.env.scoreboard] Check failed item.d_data == upload_addr_q.pop_front() (9175816 [0x8c0308] vs 0 [0x0])
  UVM_ERROR @ 2626601825 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x77 [1110111] vs 0xa3 [10100011]) addr 0x4f67d00 read out mismatch
  UVM_ERROR @ 2626601825 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0xa3 [10100011] vs 0x0 [0]) addr 0x4f67d01 read out mismatch
  UVM_ERROR @ 2626601825 ps: (mem_model.sv:48) [exp_mem_spi_device_reg_block] Check failed act_data === system_memory[addr] (0x0 [0] vs 0x6 [110]) addr 0x4f67d02 read out mismatch

UVM_ERROR (mem_model.sv:35) [rx_mem] read from uninitialized addr * has 1 failures:

Test spi_device_stress_all has 1 failures.

23.spi_device_stress_all.25508852399250386905284131318740807730569016745891359514365043464347868274733
Line 329, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/23.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 1335742078518 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x153
  UVM_ERROR @ 1335742078518 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x152
  UVM_ERROR @ 1335742078518 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x151
  UVM_ERROR @ 1335742078518 ps: (mem_model.sv:35) [rx_mem] read from uninitialized addr 0x150
  UVM_ERROR @ 1335742078518 ps: (spi_device_scoreboard.sv:985) [uvm_test_top.env.scoreboard] Check failed item.d_data == data_exp (2857933546 [0xaa589aea] vs 663676299 [0x278ee58b]) Compare SPI RX data, addr: 0x150

UVM_ERROR (spi_device_pass_base_vseq.sv:641) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_all has 1 failures.

29.spi_device_flash_all.113478790535901824394205494028715861811332970307231292827157538960693760011483
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/29.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 7686141065 ps: (spi_device_pass_base_vseq.sv:641) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 8630711800 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 2/4
  UVM_INFO @ 13322732245 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/4
  UVM_INFO @ 17533327416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_scoreboard.sv:436) scoreboard [scoreboard] Compare TPM reg failed, offset: *, act: *, exp: '{*} has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

41.spi_device_flash_and_tpm_min_idle.64308761031756719405949335869280070005756741443436242249609413379708810781172
Line 250, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 108870138 ps: (spi_device_scoreboard.sv:436) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare TPM reg failed, offset: 3, act: 0x71, exp: '{'hff}
  UVM_FATAL @ 180075138 ps: (spi_device_scoreboard.sv:1165) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 180075138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (spi_device_base_vseq.sv:398) [spi_device_fifo_underflow_overflow_vseq] wait_for_tx_avail_bytes::SramSpaceAvail has 1 failures:
- Test spi_device_stress_all has 1 failures.
  - 44.spi_device_stress_all.38752505995779456845178532601832884582375251408181354903676560066341351800599
    Line 273, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/44.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 1707648253477 ps: (spi_device_base_vseq.sv:398) [uvm_test_top.env.virtual_sequencer.spi_device_fifo_underflow_overflow_vseq] wait_for_tx_avail_bytes::SramSpaceAvail
  UVM_INFO @ 1707648253477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job spi_device-sim-vcs_run_default killed due to: Exit reason: Job lost from admin server: generic::not_found: generic::not_found: job is not found has 1 failures:
- Test spi_device_rx_timeout has 1 failures.
  - 47.spi_device_rx_timeout.60718208915941072627459851718194585588285979325362826150422302004660408677480
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/47.spi_device_rx_timeout/latest/run.log
```
  Job ID: smart:746f27f8-5e5d-413b-a326-e05c66c28988
```
UVM_FATAL (spi_device_scoreboard.sv:890) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 48.spi_device_flash_mode.92951366124160361034245648353368942601125726144176152470894073881559514635183
    Line 248, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/48.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 114994316777 ps: (spi_device_scoreboard.sv:890) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 114994316777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```