SPI_DEVICE Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: `17d5a97c3b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke			0	0	--
V1	csr_hw_reset	spi_device_csr_hw_reset	1.450s	75.156us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.610s	350.628us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.330s	2.240ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	26.740s	8.498ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.800s	60.547us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.610s	350.628us	20	20	100.00
		spi_device_csr_aliasing	26.740s	8.498ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.710s	14.840us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.770s	52.954us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	base_random_seq	spi_device_txrx			0	0	--
V2	fifo_full	spi_device_fifo_full			0	0	--
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow			0	0	--
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly			0	0	--
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly			0	0	--
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset			0	0	--
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset			0	0	--
V2	interrupts	spi_device_intr			0	0	--
V2	abort	spi_device_abort			0	0	--
V2	byte_transfer_on_spi	spi_device_byte_transfer			0	0	--
V2	rx_timeout	spi_device_rx_timeout			0	0	--
V2	bit_transfer_on_spi	spi_device_bit_transfer			0	0	--
V2	extreme_fifo_setting	spi_device_extreme_fifo_size			0	0	--
V2	perf	spi_device_perf			0	0	--
V2	csb_read	spi_device_csb_read	0.890s	64.226us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.090s	35.562us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.820s	15.142us	19	20	95.00
V2	tpm_read	spi_device_tpm_rw	14.840s	1.722ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	14.840s	1.722ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	30.090s	11.499ms	50	50	100.00
		spi_device_tpm_sts_read	1.180s	124.495us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.701m	182.897ms	48	50	96.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	45.990s	119.726ms	50	50	100.00
		spi_device_flash_all	7.408m	395.972ms	45	50	90.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	55.580s	18.627ms	50	50	100.00
		spi_device_flash_all	7.408m	395.972ms	45	50	90.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	55.580s	18.627ms	50	50	100.00
		spi_device_flash_all	7.408m	395.972ms	45	50	90.00
V2	cmd_info_slots	spi_device_flash_all	7.408m	395.972ms	45	50	90.00
V2	cmd_read_status	spi_device_intercept	14.190s	16.093ms	50	50	100.00
		spi_device_flash_all	7.408m	395.972ms	45	50	90.00
V2	cmd_read_jedec	spi_device_intercept	14.190s	16.093ms	50	50	100.00
		spi_device_flash_all	7.408m	395.972ms	45	50	90.00
V2	cmd_read_sfdp	spi_device_intercept	14.190s	16.093ms	50	50	100.00
		spi_device_flash_all	7.408m	395.972ms	45	50	90.00
V2	cmd_fast_read	spi_device_intercept	14.190s	16.093ms	50	50	100.00
		spi_device_flash_all	7.408m	395.972ms	45	50	90.00
V2	flash_cmd_upload	spi_device_upload	58.400s	186.084ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.151m	23.298ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.151m	23.298ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.151m	23.298ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	57.370s	43.957ms	47	50	94.00
		spi_device_read_buffer_direct	7.960s	7.637ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.151m	23.298ms	50	50	100.00
		spi_device_flash_all	7.408m	395.972ms	45	50	90.00
V2	quad_spi	spi_device_flash_all	7.408m	395.972ms	45	50	90.00
V2	dual_spi	spi_device_flash_all	7.408m	395.972ms	45	50	90.00
V2	4b_3b_feature	spi_device_cfg_cmd	12.260s	3.896ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	12.260s	3.896ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.589m	115.766ms	48	50	96.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	16.109m	254.743ms	46	50	92.00
V2	stress_all	spi_device_stress_all	21.950m	376.214ms	44	50	88.00
V2	alert_test	spi_device_alert_test	0.800s	40.640us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	59.357us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.950s	882.396us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.950s	882.396us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.450s	75.156us	5	5	100.00
		spi_device_csr_rw	2.610s	350.628us	20	20	100.00
		spi_device_csr_aliasing	26.740s	8.498ms	5	5	100.00
		spi_device_same_csr_outstanding	4.240s	1.106ms	19	20	95.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.450s	75.156us	5	5	100.00
		spi_device_csr_rw	2.610s	350.628us	20	20	100.00
		spi_device_csr_aliasing	26.740s	8.498ms	5	5	100.00
		spi_device_same_csr_outstanding	4.240s	1.106ms	19	20	95.00
V2		TOTAL			1006	1030	97.67
V2S	tl_intg_err	spi_device_sec_cm	1.220s	85.706us	5	5	100.00
		spi_device_tl_intg_err	21.760s	3.736ms	19	20	95.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.760s	3.736ms	19	20	95.00
V2S		TOTAL			24	25	96.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1095	1120	97.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	7	7	87.50
V2	36	23	15	41.67
V2S	2	2	1	50.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.34	98.54	94.89	98.60	90.20	97.31	96.54	98.29

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: * has 6 failures:

Test spi_device_stress_all has 3 failures.

10.spi_device_stress_all.564796330046924620446213408501320768031420179053176767374748389970974702197
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/10.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 4507269541 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 4849807660 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/11
  UVM_INFO @ 5438807071 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 5/11
  UVM_INFO @ 6622728964 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 6/11
  UVM_INFO @ 7749343222 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 7/11

28.spi_device_stress_all.52938527770397470076968333658908897986425539546560211558630869892382598469339
Line 294, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/28.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 16584182317 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 16740522317 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 17020162317 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 6/17
  UVM_ERROR @ 17096522317 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 17100605317 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 7/13

... and 1 more failures.

Test spi_device_flash_and_tpm has 1 failures.

12.spi_device_flash_and_tpm.24359959133504168061678736817563524093468517825979198990254120700271585092404
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/12.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 2537209540 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 2849518540 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 5/12
  UVM_INFO @ 3261649540 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 8/18
  UVM_INFO @ 3405145040 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 6/12
  UVM_INFO @ 3786269540 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 9/18

Test spi_device_flash_all has 1 failures.

25.spi_device_flash_all.71722509736670374291735853688704706148878788649229627176252951159638220238923
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/25.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 102650005441 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 128129034333 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 11/17
  UVM_INFO @ 143569634205 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 12/17
  UVM_INFO @ 155941045843 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 13/17
  UVM_INFO @ 174103001551 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 14/17

Test spi_device_flash_and_tpm_min_idle has 1 failures.

47.spi_device_flash_and_tpm_min_idle.80668533084355211787579560225833508633185445013336181090217100553597324273262
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 9314264291 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_INFO @ 9321864367 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 4/20
  UVM_ERROR @ 9433338209 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 10117508687 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0
  UVM_ERROR @ 10254491875 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.cfg.addr_4b_en reset value: 0x0

UVM_ERROR (spi_device_scoreboard.sv:1043) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 3 failures:
- Test spi_device_flash_mode has 3 failures.
  - 10.spi_device_flash_mode.18280007449571204267574359256136517836942238350655710127530164843651821351386
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/10.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 214918211 ps: (spi_device_scoreboard.sv:1043) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 1802661311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.spi_device_flash_mode.37378113862588845230262224164920747231020460099195428194546471985408118921623
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/17.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 4725247679 ps: (spi_device_scoreboard.sv:1043) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 10806259831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (spi_device_scoreboard.sv:487) scoreboard [scoreboard] flash_status mismatch, backdoor value: *, exp: * has 3 failures:

Test spi_device_flash_all has 3 failures.

10.spi_device_flash_all.48415642104803126488917065577609439971563497386672142133607887827486714926025
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/10.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 30425910708 ps: (spi_device_scoreboard.sv:487) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0xb3bc3e, exp: 0x119822
  UVM_ERROR @ 30425910708 ps: (spi_device_scoreboard.sv:487) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0xb3bc3e, exp: 0x119822
  UVM_INFO @ 31533243096 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 6/14
  UVM_INFO @ 34365391336 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 7/14
  UVM_INFO @ 41883417832 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 8/14

17.spi_device_flash_all.59555037907245866920124308994308622981445966170323304288333277062316122920615
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/17.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 3378785968 ps: (spi_device_scoreboard.sv:487) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0x4b2f52, exp: 0xd47088
  UVM_ERROR @ 3378785968 ps: (spi_device_scoreboard.sv:487) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] flash_status mismatch, backdoor value: 0x4b2f52, exp: 0xd47088
  UVM_INFO @ 3415396941 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 2/8
  UVM_INFO @ 6642026371 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/8
  UVM_INFO @ 7508638091 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/8

... and 1 more failures.

Job spi_device-sim-vcs_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 2 failures:
- Test spi_device_same_csr_outstanding has 1 failures.
  - 7.spi_device_same_csr_outstanding.33624969517651803131457403884472387730280229407272019218380661139726593891712
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/7.spi_device_same_csr_outstanding/latest/run.log
```
  Job ID: smart:1136093d-e194-4cae-827c-d7afa9958dd0
```
- Test spi_device_tl_intg_err has 1 failures.
  - 9.spi_device_tl_intg_err.19501994871670912812301639722400448012704051745533545889240935041506801850456
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/9.spi_device_tl_intg_err/latest/run.log
```
  Job ID: smart:b9caa76f-f818-4e38-a8c7-97536c16e680
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'addr_4b_en' while register 'spi_device_reg_block.cfg' is being accessed has 2 failures:

Test spi_device_stress_all has 2 failures.

23.spi_device_stress_all.93715608727524858351978349555648813077851893212331358814637454794526340330635
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/23.spi_device_stress_all/latest/run.log

  UVM_WARNING @ 3429140883 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'addr_4b_en' while register 'spi_device_reg_block.cfg' is being accessed
  UVM_INFO @ 3626735883 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 5/19
  UVM_INFO @ 3860540883 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 7/13
  UVM_INFO @ 4578286883 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 6/19
  UVM_INFO @ 4803100883 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 8/13

26.spi_device_stress_all.45442400299184868545206002764075401319016880119805333549455325382408335969379
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/26.spi_device_stress_all/latest/run.log

  UVM_WARNING @ 660917008 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'addr_4b_en' while register 'spi_device_reg_block.cfg' is being accessed
  UVM_INFO @ 769334808 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 3/8
  UVM_INFO @ 1038487150 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 4/8
  UVM_INFO @ 1167322868 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/7
  UVM_INFO @ 1517438680 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 5/8

Job spi_device-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test spi_device_ram_cfg has 1 failures.
  - 12.spi_device_ram_cfg.9919447986405603923521809690643704891360339263121248410865175668794935545946
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/12.spi_device_ram_cfg/latest/run.log
```
  Job ID: smart:f8843385-3d37-4e55-9f44-bb297235cee9
```

UVM_ERROR (spi_device_pass_base_vseq.sv:642) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_all has 1 failures.

18.spi_device_flash_all.27701888282074676635092965318021932787801306526564268197002069504275513252188
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/18.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 22754645561 ps: (spi_device_pass_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 25839045561 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/6
  UVM_INFO @ 30261245561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (spi_device_scoreboard.sv:253) [scoreboard] Check failed tpm_read_sw_q.size == * (* [*] vs * [*]) has 1 failures:
- Test spi_device_tpm_all has 1 failures.
  - 21.spi_device_tpm_all.10065387038801346786125568891484326958977678528354496908330317934104872073496
    Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/21.spi_device_tpm_all/latest/run.log
```
  UVM_ERROR @ 718305262 ps: (spi_device_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 718305262 ps: (uvm_comparer.svh:401) [MISCMP] Miscompare for host_item: lhs = @49407 : rhs = @0
  
  Error-[NOA] Null object access
  ../src/lowrisc_dv_spi_device_env_0.1/spi_device_scoreboard.sv, 299
```

UVM_ERROR (spi_device_scoreboard.sv:1043) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadNotEmpty mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

23.spi_device_flash_and_tpm_min_idle.112369622633284659248061017862494980880533452535850343865736078019896915504725
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 10609702878 ps: (spi_device_scoreboard.sv:1043) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadNotEmpty mismatch, act (0x0) != exp 1
  UVM_ERROR @ 10609702878 ps: (spi_device_scoreboard.sv:1043) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare CmdFifoNotEmpty mismatch, act (0x0) != exp 1
  UVM_INFO @ 10653702702 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 2/20
  UVM_INFO @ 15084698344 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 2/19
  UVM_INFO @ 25191311218 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 3/20

UVM_ERROR (spi_device_scoreboard.sv:1043) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

37.spi_device_flash_and_tpm_min_idle.13438716428607170077464178631447826626690997291904743457364739188923187798619
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 24720886395 ps: (spi_device_scoreboard.sv:1043) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 25501645455 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 6/16
  UVM_INFO @ 28936985319 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 7/15
  UVM_INFO @ 29686509935 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 7/16
  UVM_INFO @ 31428534551 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 8/15

Job spi_device-sim-vcs_run_default killed due to: Exit reason: Job lost from admin server: generic::not_found: generic::not_found: job is not found has 1 failures:
- Test spi_device_stress_all has 1 failures.
  - 39.spi_device_stress_all.31261532278453099441532955982011785527817859553135200576844005651737754878343
    Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/39.spi_device_stress_all/latest/run.log
```
  Job ID: smart:aa9a24f7-7335-4a78-ac37-6802e3b4936c
```

UVM_ERROR (spi_device_scoreboard.sv:828) scoreboard [scoreboard] Compare failed, downstream item: has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

42.spi_device_flash_and_tpm.108439259205042295337843726541636048843218228439631788213108598491927053601400
Line 253, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/42.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 1853242352 ps: (spi_device_scoreboard.sv:828) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare failed, downstream item:
  -------------------------------------------------------------
  Name                   Type              Size  Value
  -------------------------------------------------------------
  host_item              spi_item          -     @55290

UVM_ERROR (spi_device_pass_base_vseq.sv:642) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

46.spi_device_flash_and_tpm_min_idle.10944850621896478159085519423075943088063442088364313912217467850627774608508
Line 270, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 85065361969 ps: (spi_device_pass_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 85098362035 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 12/19
  UVM_INFO @ 86981365801 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 13/19
  UVM_INFO @ 90141125439 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 10/19
  UVM_INFO @ 91631375101 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 14/19

UVM_ERROR (spi_device_scoreboard.sv:426) scoreboard [scoreboard] Compare TPM reg failed, offset: *, act: *, exp: '{*, *} has 1 failures:

Test spi_device_tpm_all has 1 failures.

48.spi_device_tpm_all.23807356242050060289725666968857115045147782889384405169800806061729529013950
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/48.spi_device_tpm_all/latest/run.log

  UVM_ERROR @ 1287387691 ps: (spi_device_scoreboard.sv:426) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare TPM reg failed, offset: 0, act: 0x9f018429, exp: '{'hffffff7a, 'hffffff7a}
  UVM_FATAL @ 1288305895 ps: (spi_device_scoreboard.sv:1121) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1288305895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---