4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_smoke | 0 | 0 | -- | ||
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | spi_device_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | spi_device_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 0 | 20 | 0.00 | ||
| spi_device_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | spi_device_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | spi_device_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 65 | 0.00 | |||
| V2 | base_random_seq | spi_device_txrx | 0 | 0 | -- | ||
| V2 | fifo_full | spi_device_fifo_full | 0 | 0 | -- | ||
| V2 | fifo_underflow_overflow | spi_device_fifo_underflow_overflow | 0 | 0 | -- | ||
| V2 | dummy_sck_and_dummy_csb | spi_device_dummy_item_extra_dly | 0 | 0 | -- | ||
| V2 | extra_delay_on_spi | spi_device_dummy_item_extra_dly | 0 | 0 | -- | ||
| V2 | tx_async_fifo_reset | spi_device_tx_async_fifo_reset | 0 | 0 | -- | ||
| V2 | rx_async_fifo_reset | spi_device_rx_async_fifo_reset | 0 | 0 | -- | ||
| V2 | interrupts | spi_device_intr | 0 | 0 | -- | ||
| V2 | abort | spi_device_abort | 0 | 0 | -- | ||
| V2 | byte_transfer_on_spi | spi_device_byte_transfer | 0 | 0 | -- | ||
| V2 | rx_timeout | spi_device_rx_timeout | 0 | 0 | -- | ||
| V2 | bit_transfer_on_spi | spi_device_bit_transfer | 0 | 0 | -- | ||
| V2 | extreme_fifo_setting | spi_device_extreme_fifo_size | 0 | 0 | -- | ||
| V2 | perf | spi_device_perf | 0 | 0 | -- | ||
| V2 | csb_read | spi_device_csb_read | 0 | 50 | 0.00 | ||
| V2 | mem_parity | spi_device_mem_parity | 0 | 20 | 0.00 | ||
| V2 | mem_cfg | spi_device_ram_cfg | 0 | 20 | 0.00 | ||
| V2 | tpm_read | spi_device_tpm_rw | 0 | 50 | 0.00 | ||
| V2 | tpm_write | spi_device_tpm_rw | 0 | 50 | 0.00 | ||
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 0 | 50 | 0.00 | ||
| spi_device_tpm_sts_read | 0 | 50 | 0.00 | ||||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 0 | 50 | 0.00 | ||
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_info_slots | spi_device_flash_all | 0 | 50 | 0.00 | ||
| V2 | cmd_read_status | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_read_jedec | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_read_sfdp | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_fast_read | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | flash_cmd_upload | spi_device_upload | 0 | 50 | 0.00 | ||
| V2 | mailbox_command | spi_device_mailbox | 0 | 50 | 0.00 | ||
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 0 | 50 | 0.00 | ||
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 0 | 50 | 0.00 | ||
| V2 | cmd_read_buffer | spi_device_flash_mode | 0 | 50 | 0.00 | ||
| spi_device_read_buffer_direct | 0 | 50 | 0.00 | ||||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | quad_spi | spi_device_flash_all | 0 | 50 | 0.00 | ||
| V2 | dual_spi | spi_device_flash_all | 0 | 50 | 0.00 | ||
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 0 | 50 | 0.00 | ||
| V2 | write_enable_disable | spi_device_cfg_cmd | 0 | 50 | 0.00 | ||
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 0 | 50 | 0.00 | ||
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 0 | 50 | 0.00 | ||
| V2 | stress_all | spi_device_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | spi_device_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | spi_device_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | spi_device_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 0 | 5 | 0.00 | ||
| spi_device_csr_rw | 0 | 20 | 0.00 | ||||
| spi_device_csr_aliasing | 0 | 5 | 0.00 | ||||
| spi_device_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 0 | 5 | 0.00 | ||
| spi_device_csr_rw | 0 | 20 | 0.00 | ||||
| spi_device_csr_aliasing | 0 | 5 | 0.00 | ||||
| spi_device_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 1030 | 0.00 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 0 | 5 | 0.00 | ||
| spi_device_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 0 | 1120 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 7 | 0 | 0.00 |
| V2 | 36 | 23 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 1 | 0 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1122 failures:
0.spi_device_csb_read.24678300088101514155067482437178411499673187565669723277502696977053375573783
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_csb_read/latest/run.log
1.spi_device_csb_read.32385819854165333978554917355027645560553957964366589256812064705658760370499
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_csb_read/latest/run.log
... and 48 more failures.
0.spi_device_mem_parity.107911090857280941729537478083370254712642856524371455745933041958900604414937
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_mem_parity/latest/run.log
1.spi_device_mem_parity.103811533510080919860395864231235980984319909136381775705094093702081134556544
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_mem_parity/latest/run.log
... and 18 more failures.
0.spi_device_ram_cfg.11796588616289462192259429196292357623592230859400483917540424859100487706330
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_ram_cfg/latest/run.log
1.spi_device_ram_cfg.53427666724172744106261553973863932269799733839640069477315713151050889707283
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_ram_cfg/latest/run.log
... and 18 more failures.
0.spi_device_tpm_read_hw_reg.18979356593301112827083543489909879440331982029587004912539634630472619004672
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_tpm_read_hw_reg/latest/run.log
1.spi_device_tpm_read_hw_reg.89925153323477508035349553173937534879543383183252314849561200655285910222707
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_tpm_read_hw_reg/latest/run.log
... and 48 more failures.
0.spi_device_tpm_all.39843233569440015022547893089468628712495300696460637460676879244057291024498
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_tpm_all/latest/run.log
1.spi_device_tpm_all.7139712911834696552483704771021896718158858343140492821350640506533931027517
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_tpm_all/latest/run.log
... and 48 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.