SPI_DEVICE Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: `0dd29ab736`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke			0	0	--
V1	csr_hw_reset	spi_device_csr_hw_reset	1.380s	25.631us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.790s	116.328us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.060s	20.648ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.880s	1.243ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.610s	46.457us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.790s	116.328us	20	20	100.00
		spi_device_csr_aliasing	20.880s	1.243ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.760s	11.575us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.190s	220.426us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	base_random_seq	spi_device_txrx			0	0	--
V2	fifo_full	spi_device_fifo_full			0	0	--
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow			0	0	--
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly			0	0	--
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly			0	0	--
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset			0	0	--
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset			0	0	--
V2	interrupts	spi_device_intr			0	0	--
V2	abort	spi_device_abort			0	0	--
V2	byte_transfer_on_spi	spi_device_byte_transfer			0	0	--
V2	rx_timeout	spi_device_rx_timeout			0	0	--
V2	bit_transfer_on_spi	spi_device_bit_transfer			0	0	--
V2	extreme_fifo_setting	spi_device_extreme_fifo_size			0	0	--
V2	perf	spi_device_perf			0	0	--
V2	csb_read	spi_device_csb_read	0.820s	23.134us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.140s	39.269us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	18.949us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	5.480s	455.011us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.480s	455.011us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	36.420s	25.488ms	50	50	100.00
		spi_device_tpm_sts_read	1.380s	227.292us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	2.349m	10.460ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	49.130s	18.497ms	50	50	100.00
		spi_device_flash_all	8.160m	100.614ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	53.330s	18.656ms	50	50	100.00
		spi_device_flash_all	8.160m	100.614ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	53.330s	18.656ms	50	50	100.00
		spi_device_flash_all	8.160m	100.614ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	8.160m	100.614ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	12.900s	8.395ms	50	50	100.00
		spi_device_flash_all	8.160m	100.614ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	12.900s	8.395ms	50	50	100.00
		spi_device_flash_all	8.160m	100.614ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	12.900s	8.395ms	50	50	100.00
		spi_device_flash_all	8.160m	100.614ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	12.900s	8.395ms	50	50	100.00
		spi_device_flash_all	8.160m	100.614ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	35.080s	38.905ms	49	50	98.00
V2	mailbox_command	spi_device_mailbox	1.084m	21.578ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.084m	21.578ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.084m	21.578ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	58.690s	25.741ms	49	50	98.00
		spi_device_read_buffer_direct	7.740s	1.798ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.084m	21.578ms	50	50	100.00
		spi_device_flash_all	8.160m	100.614ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	8.160m	100.614ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	8.160m	100.614ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	14.230s	16.307ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	14.230s	16.307ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.512m	91.218ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.482m	420.115ms	49	50	98.00
V2	stress_all	spi_device_stress_all	38.133m	316.054ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.790s	24.208us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.840s	26.903us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.120s	896.228us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.120s	896.228us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.380s	25.631us	5	5	100.00
		spi_device_csr_rw	2.790s	116.328us	20	20	100.00
		spi_device_csr_aliasing	20.880s	1.243ms	5	5	100.00
		spi_device_same_csr_outstanding	4.360s	625.562us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.380s	25.631us	5	5	100.00
		spi_device_csr_rw	2.790s	116.328us	20	20	100.00
		spi_device_csr_aliasing	20.880s	1.243ms	5	5	100.00
		spi_device_same_csr_outstanding	4.360s	625.562us	20	20	100.00
V2		TOTAL			1026	1030	99.61
V2S	tl_intg_err	spi_device_sec_cm	1.170s	88.574us	5	5	100.00
		spi_device_tl_intg_err	21.920s	1.072ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.920s	1.072ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1116	1120	99.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	7	7	87.50
V2	36	23	19	52.78
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.18	98.51	94.87	98.60	89.36	97.29	96.40	98.24

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:1047) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_mode has 1 failures.

3.spi_device_flash_mode.95525084258061797070361987125306019997353803788863187999983994996265020971815
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_flash_mode/latest/run.log

  UVM_ERROR @ 526652471 ps: (spi_device_scoreboard.sv:1047) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_ERROR @ 526652471 ps: (spi_device_scoreboard.sv:1047) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 1164657535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_pass_base_vseq.sv:648) [spi_device_upload_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_upload has 1 failures.

6.spi_device_upload.23818348534802400025586931399938280360886726173071679670611035495488963243426
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/6.spi_device_upload/latest/run.log

  UVM_ERROR @ 1539021156 ps: (spi_device_pass_base_vseq.sv:648) [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 1542671156 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 11, test op = 0x54
  UVM_INFO @ 1566461156 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 12, test op = 0x3b
  UVM_INFO @ 1589656156 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 13, test op = 0xbf
  UVM_INFO @ 1592439156 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_upload_vseq] running iteration 14, test op = 0xeb

UVM_ERROR (spi_device_scoreboard.sv:425) scoreboard [scoreboard] Compare TPM reg failed, offset: *, act: *, exp: '{*} has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

37.spi_device_flash_and_tpm_min_idle.114263186644413188692123470364844645858633534978011248382561779567921557847489
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @  43595434 ps: (spi_device_scoreboard.sv:425) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare TPM reg failed, offset: 0, act: 0x16252164, exp: '{'hffffffff}
  UVM_FATAL @ 169297934 ps: (spi_device_scoreboard.sv:1126) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 169297934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_scoreboard.sv:1017) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_flash_all has 1 failures.

39.spi_device_flash_all.86924144737637414117015867681410345758487989963723491155716020192058145708378
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/39.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 6155082189 ps: (spi_device_scoreboard.sv:1017) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xe392bc) != exp '{'{other_status:'h38e4af, wel:'h1, busy:'h0}}
  UVM_INFO @ 6852439189 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 2/4
  UVM_INFO @ 11429882189 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/4
  UVM_INFO @ 14937522189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---