SPI_DEVICE Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: `5c87d18988`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke			0	0	--
V1	csr_hw_reset	spi_device_csr_hw_reset	1.550s	188.985us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.860s	198.034us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	36.050s	21.919ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	22.940s	640.397us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.530s	124.783us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.860s	198.034us	20	20	100.00
		spi_device_csr_aliasing	22.940s	640.397us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	14.040us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.130s	315.575us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	base_random_seq	spi_device_txrx			0	0	--
V2	fifo_full	spi_device_fifo_full			0	0	--
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow			0	0	--
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly			0	0	--
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly			0	0	--
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset			0	0	--
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset			0	0	--
V2	interrupts	spi_device_intr			0	0	--
V2	abort	spi_device_abort			0	0	--
V2	byte_transfer_on_spi	spi_device_byte_transfer			0	0	--
V2	rx_timeout	spi_device_rx_timeout			0	0	--
V2	bit_transfer_on_spi	spi_device_bit_transfer			0	0	--
V2	extreme_fifo_setting	spi_device_extreme_fifo_size			0	0	--
V2	perf	spi_device_perf			0	0	--
V2	csb_read	spi_device_csb_read	0.890s	19.013us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.100s	91.642us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	30.819us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	10.920s	1.006ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.920s	1.006ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	38.490s	15.395ms	50	50	100.00
		spi_device_tpm_sts_read	1.120s	563.626us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	3.059m	19.063ms	49	50	98.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	40.690s	13.960ms	50	50	100.00
		spi_device_flash_all	6.309m	76.611ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	34.740s	47.161ms	50	50	100.00
		spi_device_flash_all	6.309m	76.611ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	34.740s	47.161ms	50	50	100.00
		spi_device_flash_all	6.309m	76.611ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.309m	76.611ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	19.700s	21.058ms	50	50	100.00
		spi_device_flash_all	6.309m	76.611ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	19.700s	21.058ms	50	50	100.00
		spi_device_flash_all	6.309m	76.611ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	19.700s	21.058ms	50	50	100.00
		spi_device_flash_all	6.309m	76.611ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	19.700s	21.058ms	50	50	100.00
		spi_device_flash_all	6.309m	76.611ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	23.330s	23.084ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	57.330s	133.492ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	57.330s	133.492ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	57.330s	133.492ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.157m	13.807ms	47	50	94.00
		spi_device_read_buffer_direct	7.180s	3.207ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	57.330s	133.492ms	50	50	100.00
		spi_device_flash_all	6.309m	76.611ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.309m	76.611ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.309m	76.611ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	8.240s	1.692ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	8.240s	1.692ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.790m	507.123ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.442m	98.469ms	50	50	100.00
V2	stress_all	spi_device_stress_all	20.305m	1.148s	49	50	98.00
V2	alert_test	spi_device_alert_test	0.770s	63.710us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	57.284us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.800s	194.407us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.800s	194.407us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.550s	188.985us	5	5	100.00
		spi_device_csr_rw	2.860s	198.034us	20	20	100.00
		spi_device_csr_aliasing	22.940s	640.397us	5	5	100.00
		spi_device_same_csr_outstanding	4.190s	1.605ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.550s	188.985us	5	5	100.00
		spi_device_csr_rw	2.860s	198.034us	20	20	100.00
		spi_device_csr_aliasing	22.940s	640.397us	5	5	100.00
		spi_device_same_csr_outstanding	4.190s	1.605ms	20	20	100.00
V2		TOTAL			1024	1030	99.42
V2S	tl_intg_err	spi_device_sec_cm	1.220s	1.060ms	5	5	100.00
		spi_device_tl_intg_err	24.010s	1.148ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.010s	1.148ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1114	1120	99.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	7	7	87.50
V2	36	23	19	52.78
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.18	98.50	94.92	98.60	89.36	97.30	96.40	98.14

Failure Buckets

UVM_FATAL (spi_device_scoreboard.sv:884) [scoreboard] timeout occurred! has 2 failures:
- Test spi_device_flash_mode has 2 failures.
  - 25.spi_device_flash_mode.5367009319947420823669132593635020992874832809382343599248168262422743911590
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/25.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 236522647749 ps: (spi_device_scoreboard.sv:884) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 236522647749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.spi_device_flash_mode.64856704741150376022367675161461009563983095582325540257899738940687903152635
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/38.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 38822099887 ps: (spi_device_scoreboard.sv:884) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 38822099887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:1017) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

30.spi_device_flash_and_tpm.40095857316556676899666848141456194572407564151625214300871753991907540789074
Line 287, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/30.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 73235193248 ps: (spi_device_scoreboard.sv:1017) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3dd0bc) != exp '{'{other_status:'h345a5c, wel:'h0, busy:'h0}}
  UVM_INFO @ 73689223627 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 19/20
  UVM_INFO @ 78327107753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_scoreboard.sv:425) scoreboard [scoreboard] Compare TPM reg failed, offset: *, act: *, exp: '{*} has 1 failures:

Test spi_device_tpm_all has 1 failures.

35.spi_device_tpm_all.103184885872483688883827420201479596818680937315344435160724011394494973475633
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/35.spi_device_tpm_all/latest/run.log

  UVM_ERROR @ 1198264370 ps: (spi_device_scoreboard.sv:425) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare TPM reg failed, offset: 1, act: 0xe4f9d, exp: '{'hffffff}
  UVM_FATAL @ 1209001529 ps: (spi_device_scoreboard.sv:1126) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1209001529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_scoreboard.sv:425) scoreboard [scoreboard] Compare TPM reg failed, offset: *, act: *, exp: '{*, *} has 1 failures:

Test spi_device_stress_all has 1 failures.

42.spi_device_stress_all.98427551182017338797684138758212930629453835718375028820881717215472366082890
Line 295, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/42.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 21701035842 ps: (spi_device_scoreboard.sv:425) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare TPM reg failed, offset: 0, act: 0x7a81d6a0, exp: '{'hffffff73, 'hffffffe8}
  UVM_FATAL @ 21733885817 ps: (spi_device_scoreboard.sv:1126) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 21733885817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_scoreboard.sv:1047) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 48.spi_device_flash_mode.40767423075573188555122187372454705131039081822118670221532834934479442922537
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/48.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 1738428302 ps: (spi_device_scoreboard.sv:1047) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 1919948302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```