93b7cb99d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_smoke | 0 | 0 | -- | ||
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | spi_device_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | spi_device_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 0 | 20 | 0.00 | ||
| spi_device_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | spi_device_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | spi_device_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 65 | 0.00 | |||
| V2 | base_random_seq | spi_device_txrx | 0 | 0 | -- | ||
| V2 | fifo_full | spi_device_fifo_full | 0 | 0 | -- | ||
| V2 | fifo_underflow_overflow | spi_device_fifo_underflow_overflow | 0 | 0 | -- | ||
| V2 | dummy_sck_and_dummy_csb | spi_device_dummy_item_extra_dly | 0 | 0 | -- | ||
| V2 | extra_delay_on_spi | spi_device_dummy_item_extra_dly | 0 | 0 | -- | ||
| V2 | tx_async_fifo_reset | spi_device_tx_async_fifo_reset | 0 | 0 | -- | ||
| V2 | rx_async_fifo_reset | spi_device_rx_async_fifo_reset | 0 | 0 | -- | ||
| V2 | interrupts | spi_device_intr | 0 | 0 | -- | ||
| V2 | abort | spi_device_abort | 0 | 0 | -- | ||
| V2 | byte_transfer_on_spi | spi_device_byte_transfer | 0 | 0 | -- | ||
| V2 | rx_timeout | spi_device_rx_timeout | 0 | 0 | -- | ||
| V2 | bit_transfer_on_spi | spi_device_bit_transfer | 0 | 0 | -- | ||
| V2 | extreme_fifo_setting | spi_device_extreme_fifo_size | 0 | 0 | -- | ||
| V2 | perf | spi_device_perf | 0 | 0 | -- | ||
| V2 | csb_read | spi_device_csb_read | 0 | 50 | 0.00 | ||
| V2 | mem_parity | spi_device_mem_parity | 0 | 20 | 0.00 | ||
| V2 | mem_cfg | spi_device_ram_cfg | 0 | 20 | 0.00 | ||
| V2 | tpm_read | spi_device_tpm_rw | 0 | 50 | 0.00 | ||
| V2 | tpm_write | spi_device_tpm_rw | 0 | 50 | 0.00 | ||
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 0 | 50 | 0.00 | ||
| spi_device_tpm_sts_read | 0 | 50 | 0.00 | ||||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 0 | 50 | 0.00 | ||
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_info_slots | spi_device_flash_all | 0 | 50 | 0.00 | ||
| V2 | cmd_read_status | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_read_jedec | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_read_sfdp | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | cmd_fast_read | spi_device_intercept | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | flash_cmd_upload | spi_device_upload | 0 | 50 | 0.00 | ||
| V2 | mailbox_command | spi_device_mailbox | 0 | 50 | 0.00 | ||
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 0 | 50 | 0.00 | ||
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 0 | 50 | 0.00 | ||
| V2 | cmd_read_buffer | spi_device_flash_mode | 0 | 50 | 0.00 | ||
| spi_device_read_buffer_direct | 0 | 50 | 0.00 | ||||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 0 | 50 | 0.00 | ||
| spi_device_flash_all | 0 | 50 | 0.00 | ||||
| V2 | quad_spi | spi_device_flash_all | 0 | 50 | 0.00 | ||
| V2 | dual_spi | spi_device_flash_all | 0 | 50 | 0.00 | ||
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 0 | 50 | 0.00 | ||
| V2 | write_enable_disable | spi_device_cfg_cmd | 0 | 50 | 0.00 | ||
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 0 | 50 | 0.00 | ||
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 0 | 50 | 0.00 | ||
| V2 | stress_all | spi_device_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | spi_device_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | spi_device_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | spi_device_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 0 | 5 | 0.00 | ||
| spi_device_csr_rw | 0 | 20 | 0.00 | ||||
| spi_device_csr_aliasing | 0 | 5 | 0.00 | ||||
| spi_device_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 0 | 5 | 0.00 | ||
| spi_device_csr_rw | 0 | 20 | 0.00 | ||||
| spi_device_csr_aliasing | 0 | 5 | 0.00 | ||||
| spi_device_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 1030 | 0.00 | |||
| V2S | tl_intg_err | spi_device_sec_cm | 0 | 5 | 0.00 | ||
| spi_device_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 0 | 1120 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 7 | 0 | 0.00 |
| V2 | 36 | 23 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 1 | 0 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1122 failures:
0.spi_device_csb_read.32813748893774195109253246487075154293677754469661897896605859241039164360416
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_csb_read/latest/run.log
1.spi_device_csb_read.14511808992371121978486084484212046428802103095417512364980752215536740692134
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_csb_read/latest/run.log
... and 48 more failures.
0.spi_device_mem_parity.77861804083604472429303366821104731262360604383732677601382054316742011903873
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_mem_parity/latest/run.log
1.spi_device_mem_parity.49547383701313277593700080253280265732755309092604372399003940950505220924186
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_mem_parity/latest/run.log
... and 18 more failures.
0.spi_device_ram_cfg.82062109488869151574056443407900021754045725904209535563630002226254948019911
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_ram_cfg/latest/run.log
1.spi_device_ram_cfg.66041626421104537629626548673453059660475758518849377040492822279753310249534
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_ram_cfg/latest/run.log
... and 18 more failures.
0.spi_device_tpm_read_hw_reg.28786754980746642997161868648599599241049561876217247803354947603416562703478
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_tpm_read_hw_reg/latest/run.log
1.spi_device_tpm_read_hw_reg.68848653573565724021618540595818384858820005338444784462768026147467612983909
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_tpm_read_hw_reg/latest/run.log
... and 48 more failures.
0.spi_device_tpm_all.15772104859967771815339790844892951156025823059448067292383052334096034991904
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_tpm_all/latest/run.log
1.spi_device_tpm_all.63764557339889776653072465140100120762574168448103195940164132556542830412051
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_tpm_all/latest/run.log
... and 48 more failures.
Job spi_device-sim-vcs_build_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
default
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/default/build.log
Job ID: smart:58b23602-671d-47a6-80f9-362de824b837
Job spi_device-sim-vcs_build_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
cover_reg_top
Log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/cover_reg_top/build.log
Job ID: smart:38c4e7d6-17d8-44e2-adb3-bed3ab7279d4