SPI_DEVICE Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke			0	0	--
V1	csr_hw_reset	spi_device_csr_hw_reset	1.450s	80.640us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.630s	203.452us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.120s	21.406ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.290s	958.194us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	10.210s	539.976us	12	20	60.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.630s	203.452us	20	20	100.00
		spi_device_csr_aliasing	24.290s	958.194us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	29.273us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.230s	58.081us	5	5	100.00
V1		TOTAL			57	65	87.69
V2	base_random_seq	spi_device_txrx			0	0	--
V2	fifo_full	spi_device_fifo_full			0	0	--
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow			0	0	--
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly			0	0	--
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly			0	0	--
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset			0	0	--
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset			0	0	--
V2	interrupts	spi_device_intr			0	0	--
V2	abort	spi_device_abort			0	0	--
V2	byte_transfer_on_spi	spi_device_byte_transfer			0	0	--
V2	rx_timeout	spi_device_rx_timeout			0	0	--
V2	bit_transfer_on_spi	spi_device_bit_transfer			0	0	--
V2	extreme_fifo_setting	spi_device_extreme_fifo_size			0	0	--
V2	perf	spi_device_perf			0	0	--
V2	csb_read	spi_device_csb_read	0.850s	18.782us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.120s	25.698us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.790s	15.165us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	13.310s	328.219us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	13.310s	328.219us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	33.990s	44.321ms	50	50	100.00
		spi_device_tpm_sts_read	1.200s	153.222us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.908m	18.085ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	49.230s	15.207ms	50	50	100.00
		spi_device_flash_all	3.945m	98.685ms	47	50	94.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	40.300s	59.107ms	50	50	100.00
		spi_device_flash_all	3.945m	98.685ms	47	50	94.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	40.300s	59.107ms	50	50	100.00
		spi_device_flash_all	3.945m	98.685ms	47	50	94.00
V2	cmd_info_slots	spi_device_flash_all	3.945m	98.685ms	47	50	94.00
V2	cmd_read_status	spi_device_intercept	16.500s	42.281ms	50	50	100.00
		spi_device_flash_all	3.945m	98.685ms	47	50	94.00
V2	cmd_read_jedec	spi_device_intercept	16.500s	42.281ms	50	50	100.00
		spi_device_flash_all	3.945m	98.685ms	47	50	94.00
V2	cmd_read_sfdp	spi_device_intercept	16.500s	42.281ms	50	50	100.00
		spi_device_flash_all	3.945m	98.685ms	47	50	94.00
V2	cmd_fast_read	spi_device_intercept	16.500s	42.281ms	50	50	100.00
		spi_device_flash_all	3.945m	98.685ms	47	50	94.00
V2	flash_cmd_upload	spi_device_upload	54.420s	33.674ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	54.140s	21.551ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	54.140s	21.551ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	54.140s	21.551ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	56.530s	30.654ms	48	50	96.00
		spi_device_read_buffer_direct	7.440s	2.156ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	54.140s	21.551ms	50	50	100.00
		spi_device_flash_all	3.945m	98.685ms	47	50	94.00
V2	quad_spi	spi_device_flash_all	3.945m	98.685ms	47	50	94.00
V2	dual_spi	spi_device_flash_all	3.945m	98.685ms	47	50	94.00
V2	4b_3b_feature	spi_device_cfg_cmd	14.510s	18.107ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	14.510s	18.107ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.973m	102.839ms	46	50	92.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.320m	247.221ms	47	50	94.00
V2	stress_all	spi_device_stress_all	19.027m	486.211ms	49	50	98.00
V2	alert_test	spi_device_alert_test	0.790s	42.239us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.790s	18.088us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.800s	386.559us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.800s	386.559us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.450s	80.640us	5	5	100.00
		spi_device_csr_rw	2.630s	203.452us	20	20	100.00
		spi_device_csr_aliasing	24.290s	958.194us	5	5	100.00
		spi_device_same_csr_outstanding	4.550s	475.834us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.450s	80.640us	5	5	100.00
		spi_device_csr_rw	2.630s	203.452us	20	20	100.00
		spi_device_csr_aliasing	24.290s	958.194us	5	5	100.00
		spi_device_same_csr_outstanding	4.550s	475.834us	20	20	100.00
V2		TOTAL			1017	1030	98.74
V2S	tl_intg_err	spi_device_sec_cm	1.170s	110.080us	5	5	100.00
		spi_device_tl_intg_err	21.980s	6.884ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.980s	6.884ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1099	1120	98.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	7	6	75.00
V2	36	23	18	50.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.17	98.50	94.91	98.60	89.36	97.30	96.40	98.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:756) [spi_device_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 8 failures:

Test spi_device_csr_mem_rw_with_rand_reset has 8 failures.

3.spi_device_csr_mem_rw_with_rand_reset.17995031774597262764896913705112532781891421960708445867064709534109374570462
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 929197669 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_ERROR @ 929203183 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 929203183 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq]
  Reset is issued for run 1/1
  UVM_INFO @ 930112273 ps: (cip_base_vseq.sv:725) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq]

8.spi_device_csr_mem_rw_with_rand_reset.90856559229219512019248995702938569687304486645831544366981167191838603142152
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 228085914 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_ERROR @ 228088428 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 228088428 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq]
  Reset is issued for run 2/2
  UVM_INFO @ 228130096 ps: (cip_base_vseq.sv:725) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq]

... and 6 more failures.

UVM_ERROR (spi_device_scoreboard.sv:1017) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 3 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

10.spi_device_flash_and_tpm_min_idle.6617397082257529922670775863427195924076646832725670272169762546191711283599
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 1426611581 ps: (spi_device_scoreboard.sv:1017) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5621dc) != exp '{'{other_status:'h2c2cad, wel:'h0, busy:'h0}}
  UVM_INFO @ 1430591581 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 3/10
  UVM_INFO @ 1885443581 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 3/19
  UVM_INFO @ 1930441581 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 4/10
  UVM_INFO @ 2438923581 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 4/19

Test spi_device_flash_and_tpm has 1 failures.

26.spi_device_flash_and_tpm.22655689091519389271301364609053044667464532472089882025584687751503276291996
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/26.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 31177956429 ps: (spi_device_scoreboard.sv:1017) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x3136e8) != exp '{'{other_status:'h2bffc3, wel:'h0, busy:'h0}}
  UVM_INFO @ 35187596429 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 7/10
  UVM_INFO @ 36291670429 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 6/12
  UVM_INFO @ 43068796429 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 8/10
  UVM_INFO @ 45361050429 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 7/12

Test spi_device_flash_all has 1 failures.

45.spi_device_flash_all.39705732488358280022347292388363581758752104139785377210055928193702350777817
Line 255, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/45.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 12226473685 ps: (spi_device_scoreboard.sv:1017) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x4335b0) != exp '{'{other_status:'h28ac01, wel:'h0, busy:'h0}}
  UVM_INFO @ 13146929685 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 6/17
  UVM_INFO @ 16061686685 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 7/17
  UVM_INFO @ 17183290685 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 8/17
  UVM_INFO @ 19644633685 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 9/17

Exit reason: Error: User command failed UVM_ERROR (spi_device_scoreboard.sv:252) [scoreboard] Check failed tpm_read_sw_q.size == * (* [*] vs * [*]) has 2 failures:

Test spi_device_flash_and_tpm has 1 failures.

14.spi_device_flash_and_tpm.37582699675853274350316587816585756884471742829190275791232733147081132649048
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/14.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 1301127604 ps: (spi_device_scoreboard.sv:252) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1301127604 ps: (uvm_comparer.svh:401) [MISCMP] Miscompare for host_item: lhs = @175929 : rhs = @0
  
  Error-[NOA] Null object access
  ../src/lowrisc_dv_spi_device_env_0.1/spi_device_scoreboard.sv, 298

Test spi_device_stress_all has 1 failures.

17.spi_device_stress_all.34702881059898837151039466909141583432672574371559615697510436974086658571693
Line 285, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/17.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 15138215878 ps: (spi_device_scoreboard.sv:252) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 15138215878 ps: (uvm_comparer.svh:401) [MISCMP] Miscompare for host_item: lhs = @646630 : rhs = @0
  
  Error-[NOA] Null object access
  ../src/lowrisc_dv_spi_device_env_0.1/spi_device_scoreboard.sv, 298

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 2 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

19.spi_device_flash_and_tpm_min_idle.5706875082197134890651110240774175931177463231664771077095751489919987977639
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 7314726909 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 7451932834 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 8/15
  UVM_INFO @ 8466362036 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 9/15
  UVM_INFO @ 9274750286 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 10/15
  UVM_INFO @ 10611834127 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 11/15

Test spi_device_flash_and_tpm has 1 failures.

49.spi_device_flash_and_tpm.45494974867316815906273165560291877778588854845265285286334784894143035201866
Line 269, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/49.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 3194426917 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 3216906803 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/15
  UVM_INFO @ 3403234676 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/15
  UVM_INFO @ 3533015128 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/15
  UVM_INFO @ 3689721812 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 12/15

UVM_ERROR (spi_device_scoreboard.sv:425) scoreboard [scoreboard] Compare TPM reg failed, offset: *, act: *, exp: '{*} has 2 failures:

Test spi_device_flash_and_tpm has 1 failures.

39.spi_device_flash_and_tpm.114214609999045011380073788028932965668100871155893927221127481475112204432895
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/39.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 1533886170 ps: (spi_device_scoreboard.sv:425) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare TPM reg failed, offset: 1, act: 0x2a28de, exp: '{'hffffff}
  UVM_FATAL @ 1534887890 ps: (spi_device_scoreboard.sv:1126) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1534887890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_flash_and_tpm_min_idle has 1 failures.

39.spi_device_flash_and_tpm_min_idle.85964826222201629672787468632289806138716803305624933145043823601440708095381
Line 268, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 10361580900 ps: (spi_device_scoreboard.sv:425) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare TPM reg failed, offset: 3, act: 0xf, exp: '{'hff}
  UVM_FATAL @ 10568945900 ps: (spi_device_scoreboard.sv:1126) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 10568945900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_scoreboard.sv:1047) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_mode has 1 failures.

6.spi_device_flash_mode.85561584516310142427818942088549869197352573130177731294942227786975172126835
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/6.spi_device_flash_mode/latest/run.log

  UVM_ERROR @ 198724011 ps: (spi_device_scoreboard.sv:1047) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_ERROR @ 198724011 ps: (spi_device_scoreboard.sv:1047) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 404202359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_scoreboard.sv:472) [scoreboard] Check failed flash_status_q.size <= * (* [*] vs * [*]) has 1 failures:

Test spi_device_flash_all has 1 failures.

10.spi_device_flash_all.79702869126383406355588278778675428944161475926985279016757387719661333787887
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/10.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 48358415696 ps: (spi_device_scoreboard.sv:472) [uvm_test_top.env.scoreboard] Check failed flash_status_q.size <= 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 48892688912 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 12/17
  UVM_INFO @ 55356369916 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 13/17
  UVM_INFO @ 56710662368 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 14/17
  UVM_INFO @ 62261738124 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 15/17

UVM_ERROR (spi_device_scoreboard.sv:1047) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 24.spi_device_flash_mode.35949699292692919260826040845098189263470038223034370128947554433305113664995
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/24.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @  23604937 ps: (spi_device_scoreboard.sv:1047) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 672947727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:1047) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_all has 1 failures.

26.spi_device_flash_all.4647627253880076172759771855021785407445875538099932393126015683764429248438
Line 267, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/26.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 8865759700 ps: (spi_device_scoreboard.sv:1047) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 8913887846 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 18/19
  UVM_INFO @ 9458459080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---