SPI_DEVICE Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke			0	0	--
V1	csr_hw_reset	spi_device_csr_hw_reset	1.430s	154.152us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.720s	391.864us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.150s	549.076us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	25.520s	11.733ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	6.950s	238.811us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.720s	391.864us	20	20	100.00
		spi_device_csr_aliasing	25.520s	11.733ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	18.751us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.200s	68.310us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	base_random_seq	spi_device_txrx			0	0	--
V2	fifo_full	spi_device_fifo_full			0	0	--
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow			0	0	--
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly			0	0	--
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly			0	0	--
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset			0	0	--
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset			0	0	--
V2	interrupts	spi_device_intr			0	0	--
V2	abort	spi_device_abort			0	0	--
V2	byte_transfer_on_spi	spi_device_byte_transfer			0	0	--
V2	rx_timeout	spi_device_rx_timeout			0	0	--
V2	bit_transfer_on_spi	spi_device_bit_transfer			0	0	--
V2	extreme_fifo_setting	spi_device_extreme_fifo_size			0	0	--
V2	perf	spi_device_perf			0	0	--
V2	csb_read	spi_device_csb_read	0.900s	76.011us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.150s	88.519us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.780s	16.485us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	11.590s	215.879us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.590s	215.879us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	23.400s	7.270ms	50	50	100.00
		spi_device_tpm_sts_read	1.200s	200.459us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	2.053m	23.098ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	42.100s	16.084ms	50	50	100.00
		spi_device_flash_all	8.395m	285.336ms	48	50	96.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	51.960s	21.103ms	50	50	100.00
		spi_device_flash_all	8.395m	285.336ms	48	50	96.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	51.960s	21.103ms	50	50	100.00
		spi_device_flash_all	8.395m	285.336ms	48	50	96.00
V2	cmd_info_slots	spi_device_flash_all	8.395m	285.336ms	48	50	96.00
V2	cmd_read_status	spi_device_intercept	15.800s	29.933ms	50	50	100.00
		spi_device_flash_all	8.395m	285.336ms	48	50	96.00
V2	cmd_read_jedec	spi_device_intercept	15.800s	29.933ms	50	50	100.00
		spi_device_flash_all	8.395m	285.336ms	48	50	96.00
V2	cmd_read_sfdp	spi_device_intercept	15.800s	29.933ms	50	50	100.00
		spi_device_flash_all	8.395m	285.336ms	48	50	96.00
V2	cmd_fast_read	spi_device_intercept	15.800s	29.933ms	50	50	100.00
		spi_device_flash_all	8.395m	285.336ms	48	50	96.00
V2	flash_cmd_upload	spi_device_upload	46.950s	268.886ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	52.700s	19.108ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	52.700s	19.108ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	52.700s	19.108ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.121m	51.612ms	47	50	94.00
		spi_device_read_buffer_direct	7.710s	1.808ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	52.700s	19.108ms	50	50	100.00
		spi_device_flash_all	8.395m	285.336ms	48	50	96.00
V2	quad_spi	spi_device_flash_all	8.395m	285.336ms	48	50	96.00
V2	dual_spi	spi_device_flash_all	8.395m	285.336ms	48	50	96.00
V2	4b_3b_feature	spi_device_cfg_cmd	14.720s	3.954ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	14.720s	3.954ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.977m	354.248ms	47	50	94.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	15.129m	121.611ms	46	50	92.00
V2	stress_all	spi_device_stress_all	20.187m	170.571ms	47	50	94.00
V2	alert_test	spi_device_alert_test	0.790s	13.090us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.780s	15.031us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.960s	211.468us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.960s	211.468us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.430s	154.152us	5	5	100.00
		spi_device_csr_rw	2.720s	391.864us	20	20	100.00
		spi_device_csr_aliasing	25.520s	11.733ms	5	5	100.00
		spi_device_same_csr_outstanding	4.540s	1.203ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.430s	154.152us	5	5	100.00
		spi_device_csr_rw	2.720s	391.864us	20	20	100.00
		spi_device_csr_aliasing	25.520s	11.733ms	5	5	100.00
		spi_device_same_csr_outstanding	4.540s	1.203ms	20	20	100.00
V2		TOTAL			1015	1030	98.54
V2S	tl_intg_err	spi_device_sec_cm	1.280s	127.446us	5	5	100.00
		spi_device_tl_intg_err	21.740s	1.906ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.740s	1.906ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1105	1120	98.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	7	7	87.50
V2	36	23	18	50.00
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.18	98.50	94.91	98.60	89.36	97.31	96.40	98.19

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:472) [scoreboard] Check failed flash_status_q.size <= * (* [*] vs * [*]) has 3 failures:

Test spi_device_flash_all has 1 failures.

1.spi_device_flash_all.112623325706272648511909422807598478312304313641140453758089361075944767598651
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 10603795359 ps: (spi_device_scoreboard.sv:472) [uvm_test_top.env.scoreboard] Check failed flash_status_q.size <= 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 13208083359 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 2/15
  UVM_INFO @ 21115972359 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/15
  UVM_INFO @ 27371180359 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/15
  UVM_INFO @ 35180765359 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/15

Test spi_device_flash_and_tpm_min_idle has 1 failures.

3.spi_device_flash_and_tpm_min_idle.63068669637052624032264419006919738638238033901757875858178234409932166766746
Line 262, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 334781290418 ps: (spi_device_scoreboard.sv:472) [uvm_test_top.env.scoreboard] Check failed flash_status_q.size <= 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 338527086431 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 8/11
  UVM_INFO @ 340890006532 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 6/12
  UVM_INFO @ 358268196931 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 9/11
  UVM_INFO @ 380841522136 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 7/12

Test spi_device_stress_all has 1 failures.

30.spi_device_stress_all.107880410814789328836395990768376538712731278348461547984506904745928162137794
Line 282, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/30.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 64140626930 ps: (spi_device_scoreboard.sv:472) [uvm_test_top.env.scoreboard] Check failed flash_status_q.size <= 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 65744593814 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 15/17
  UVM_INFO @ 70311676278 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 16/17
  UVM_INFO @ 71990615150 ps: (cip_base_vseq.sv:441) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq] Running intr test iteration 1/9
  UVM_INFO @ 71991982486 ps: (cip_base_vseq.sv:441) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq] Running intr test iteration 2/9

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 3 failures:

Test spi_device_flash_and_tpm has 1 failures.

16.spi_device_flash_and_tpm.82039760878960219146265183754175982413079182489875283897030451011099113155625
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/16.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 3425123685 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 3586738332 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/20
  UVM_INFO @ 3917462829 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/20
  UVM_INFO @ 4343524482 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/20
  UVM_INFO @ 4661651916 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/20

Test spi_device_stress_all has 1 failures.

19.spi_device_stress_all.98512322456475734465196964054115730649283378647886942239261620217157601934380
Line 265, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/19.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 3275750692 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 3304586367 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/12
  UVM_INFO @ 3640842401 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/12
  UVM_INFO @ 3959401449 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/12
  UVM_INFO @ 4287564319 ps: (cip_base_vseq.sv:441) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_common_vseq] Running intr test iteration 1/3

Test spi_device_flash_and_tpm_min_idle has 1 failures.

42.spi_device_flash_and_tpm_min_idle.80946554222934267759726886217514447321494358196199631430684773636969256117557
Line 267, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 19267369525 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 20191272030 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 15/18
  UVM_INFO @ 21501387397 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 16/18
  UVM_INFO @ 22552123918 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 17/18
  UVM_INFO @ 24373292685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

UVM_ERROR (spi_device_scoreboard.sv:425) scoreboard [scoreboard] Compare TPM reg failed, offset: *, act: *, exp: '{*} has 2 failures:

Test spi_device_flash_and_tpm has 1 failures.

22.spi_device_flash_and_tpm.51915625545434863009449804641335691972470922702418516032660938572465475298248
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/22.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 788868272 ps: (spi_device_scoreboard.sv:425) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare TPM reg failed, offset: 0, act: 0xd2de75f3, exp: '{'hffffffff}
  UVM_INFO @ 824170346 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 3/11
  UVM_FATAL @ 843321327 ps: (spi_device_scoreboard.sv:1126) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 843321327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_stress_all has 1 failures.

26.spi_device_stress_all.94863800502095880449164518094874263737175159335844792636168117787803851923905
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/26.spi_device_stress_all/latest/run.log

  UVM_ERROR @  15487156 ps: (spi_device_scoreboard.sv:425) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Compare TPM reg failed, offset: 3, act: 0xad, exp: '{'hff}
  UVM_FATAL @  85387604 ps: (spi_device_scoreboard.sv:1126) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @  85387604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (spi_device_scoreboard.sv:1047) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 2 failures:
- Test spi_device_flash_mode has 2 failures.
  - 34.spi_device_flash_mode.114826361060846145218315236998025413198147082227687720340501858219663646384191
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/34.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @  20907401 ps: (spi_device_scoreboard.sv:1047) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 322457401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.spi_device_flash_mode.92418123016262701324062569954029399818930130007368932709374759034270080897832
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/44.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 263254175 ps: (spi_device_scoreboard.sv:1047) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 3326294175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (spi_device_scoreboard.sv:1047) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 12.spi_device_flash_mode.31519449089640365718933517285846625209650790881340473882759980086532205316098
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/12.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 1050214180 ps: (spi_device_scoreboard.sv:1047) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 2479651764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:856) [scoreboard] Check failed spi_passthrough_downstream_q.size == * (* [*] vs * [*]) has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

23.spi_device_flash_and_tpm.97577846367570885871875281974958828965109504718848201531590690136750345276786
Line 265, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/23.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 4200097176 ps: (spi_device_scoreboard.sv:856) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_FATAL @ 4200097177 ps: (spi_device_scoreboard.sv:819) [uvm_test_top.env.scoreboard] Check failed spi_passthrough_downstream_q.size == 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 4200097177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (spi_device_scoreboard.sv:252) [scoreboard] Check failed tpm_read_sw_q.size == * (* [*] vs * [*]) has 1 failures:
- Test spi_device_flash_and_tpm_min_idle has 1 failures.
  - 39.spi_device_flash_and_tpm_min_idle.102330366354535095764213831661178013956310031029311449326041255187503148082992
    Line 264, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  UVM_ERROR @ 1541598133 ps: (spi_device_scoreboard.sv:252) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1541598133 ps: (uvm_comparer.svh:401) [MISCMP] Miscompare for host_item: lhs = @259560 : rhs = @0
  
  Error-[NOA] Null object access
  ../src/lowrisc_dv_spi_device_env_0.1/spi_device_scoreboard.sv, 298
```

UVM_ERROR (spi_device_scoreboard.sv:1017) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

46.spi_device_flash_and_tpm_min_idle.17193923413066494265941969811063476181017881064560539651527551253436795625542
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 116976714 ps: (spi_device_scoreboard.sv:1017) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xcbc0d8) != exp '{'{other_status:'hc0c21, wel:'h0, busy:'h0}}
  UVM_INFO @ 257735486 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 1/10
  UVM_INFO @ 286831102 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 2/15
  UVM_INFO @ 629109845 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 2/10
  UVM_INFO @ 1006238626 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 3/10

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_all has 1 failures.

47.spi_device_flash_all.67653884268591509738908756199806912194987502339741896545782253262568993170312
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/47.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 4380342340 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 4870146031 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/6
  UVM_INFO @ 5437893432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---