SPI_DEVICE Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: `49a27e136c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke			0	0	--
V1	csr_hw_reset	spi_device_csr_hw_reset	1.360s	22.720us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.870s	115.320us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.040s	10.263ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.590s	1.800ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	6.600s	217.468us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.870s	115.320us	20	20	100.00
		spi_device_csr_aliasing	23.590s	1.800ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.670s	20.893us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.960s	109.903us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	base_random_seq	spi_device_txrx			0	0	--
V2	fifo_full	spi_device_fifo_full			0	0	--
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow			0	0	--
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly			0	0	--
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly			0	0	--
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset			0	0	--
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset			0	0	--
V2	interrupts	spi_device_intr			0	0	--
V2	abort	spi_device_abort			0	0	--
V2	byte_transfer_on_spi	spi_device_byte_transfer			0	0	--
V2	rx_timeout	spi_device_rx_timeout			0	0	--
V2	bit_transfer_on_spi	spi_device_bit_transfer			0	0	--
V2	extreme_fifo_setting	spi_device_extreme_fifo_size			0	0	--
V2	perf	spi_device_perf			0	0	--
V2	csb_read	spi_device_csb_read	0.850s	57.108us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.180s	150.480us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.830s	16.137us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	9.830s	374.595us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.830s	374.595us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	36.740s	51.675ms	50	50	100.00
		spi_device_tpm_sts_read	1.210s	607.018us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.259m	15.436ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	45.240s	26.362ms	50	50	100.00
		spi_device_flash_all	8.786m	453.140ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	56.240s	42.585ms	50	50	100.00
		spi_device_flash_all	8.786m	453.140ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	56.240s	42.585ms	50	50	100.00
		spi_device_flash_all	8.786m	453.140ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	8.786m	453.140ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	19.150s	22.559ms	50	50	100.00
		spi_device_flash_all	8.786m	453.140ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	19.150s	22.559ms	50	50	100.00
		spi_device_flash_all	8.786m	453.140ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	19.150s	22.559ms	50	50	100.00
		spi_device_flash_all	8.786m	453.140ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	19.150s	22.559ms	50	50	100.00
		spi_device_flash_all	8.786m	453.140ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	52.880s	34.752ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	53.630s	78.083ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	53.630s	78.083ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	53.630s	78.083ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.221m	15.469ms	47	50	94.00
		spi_device_read_buffer_direct	8.020s	3.835ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	53.630s	78.083ms	50	50	100.00
		spi_device_flash_all	8.786m	453.140ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	8.786m	453.140ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	8.786m	453.140ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	11.730s	6.739ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	11.730s	6.739ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.303m	164.973ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.523m	151.845ms	48	50	96.00
V2	stress_all	spi_device_stress_all	17.357m	904.689ms	47	50	94.00
V2	alert_test	spi_device_alert_test	0.820s	16.443us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.790s	18.448us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.930s	252.948us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.930s	252.948us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.360s	22.720us	5	5	100.00
		spi_device_csr_rw	2.870s	115.320us	20	20	100.00
		spi_device_csr_aliasing	23.590s	1.800ms	5	5	100.00
		spi_device_same_csr_outstanding	4.300s	163.470us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.360s	22.720us	5	5	100.00
		spi_device_csr_rw	2.870s	115.320us	20	20	100.00
		spi_device_csr_aliasing	23.590s	1.800ms	5	5	100.00
		spi_device_same_csr_outstanding	4.300s	163.470us	20	20	100.00
V2		TOTAL			1021	1030	99.13
V2S	tl_intg_err	spi_device_sec_cm	1.170s	103.573us	5	5	100.00
		spi_device_tl_intg_err	24.860s	10.905ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.860s	10.905ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1111	1120	99.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	7	7	87.50
V2	36	23	19	52.78
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	98.52	94.56	98.61	89.36	97.29	96.09	98.07

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:1024) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 4 failures:

Test spi_device_flash_and_tpm has 1 failures.

14.spi_device_flash_and_tpm.87677404640557391127970970693555369928776302717564379474793601929183364831511
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/14.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 581734352 ps: (spi_device_scoreboard.sv:1024) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x677ece) != exp '{'{other_status:'h2e5908, wel:'h0, busy:'h0}}
  UVM_INFO @ 596407540 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/7
  UVM_INFO @ 883303368 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/9
  UVM_INFO @ 1140104982 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/7
  UVM_INFO @ 1470359896 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/9

Test spi_device_stress_all has 1 failures.

19.spi_device_stress_all.113077417232657334702037917053926092761617598724249852586894138781240922058489
Line 303, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/19.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 37366113776 ps: (spi_device_scoreboard.sv:1024) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x602070) != exp '{'{other_status:'ha95b, wel:'h0, busy:'h0}}
  UVM_INFO @ 41201409776 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/6
  UVM_INFO @ 41268453776 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/19
  UVM_INFO @ 47374489776 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/6
  UVM_INFO @ 47389353776 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/19

Test spi_device_flash_and_tpm_min_idle has 2 failures.

29.spi_device_flash_and_tpm_min_idle.107391507352903144905072538376685359457964566132259418132649578733283425064878
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 2164422640 ps: (spi_device_scoreboard.sv:1024) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xcdd528) != exp '{'{other_status:'h2fdc85, wel:'h0, busy:'h0}}
  UVM_INFO @ 2200922569 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 4/20
  UVM_INFO @ 2384290886 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 7/12
  UVM_INFO @ 2667593534 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 8/12
  UVM_INFO @ 2687537640 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 5/20

46.spi_device_flash_and_tpm_min_idle.23770148199439642411261398377717315827905976136786100925118741370537948869351
Line 260, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 29735273206 ps: (spi_device_scoreboard.sv:1024) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x44f880) != exp '{'{other_status:'h1b4c5a, wel:'h0, busy:'h0}}
  UVM_INFO @ 30127997294 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 7/14
  UVM_INFO @ 32781699550 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 8/14
  UVM_INFO @ 37923575090 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 9/14
  UVM_INFO @ 42288682982 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 10/14

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 3 failures:
- Test spi_device_flash_mode has 3 failures.
  - 0.spi_device_flash_mode.79907944666437436359667188109762740486572339315120395181417462737701687438746
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 931890091 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 1269434418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.spi_device_flash_mode.8941148430129765000801010416330811973417305060226069282010377384982721900025
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/9.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 206050316 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 660801820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 2 failures:

Test spi_device_stress_all has 2 failures.

10.spi_device_stress_all.18020863839692449643394301127945650639662517991911016260861758258224218021673
Line 313, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/10.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 51263693844 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 51430104078 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/11
  UVM_INFO @ 51701316404 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/11
  UVM_INFO @ 52139266850 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 10/11
  UVM_INFO @ 52452394742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

25.spi_device_stress_all.13916558607497976255441117365067387424286707058246182372696254517911766911751
Line 267, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/25.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 1411338787 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 1411905782 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 5/15
  UVM_INFO @ 1578053309 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 5/7
  UVM_INFO @ 1760133493 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 6/15
  UVM_INFO @ 2098439420 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 6/7