SPI_DEVICE Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke			0	0	--
V1	csr_hw_reset	spi_device_csr_hw_reset	1.220s	123.987us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.040s	140.896us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	40.230s	2.705ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.780s	2.525ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.150s	361.708us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.040s	140.896us	20	20	100.00
		spi_device_csr_aliasing	16.780s	2.525ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.720s	16.597us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.470s	69.944us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	base_random_seq	spi_device_txrx			0	0	--
V2	fifo_full	spi_device_fifo_full			0	0	--
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow			0	0	--
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly			0	0	--
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly			0	0	--
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset			0	0	--
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset			0	0	--
V2	interrupts	spi_device_intr			0	0	--
V2	abort	spi_device_abort			0	0	--
V2	byte_transfer_on_spi	spi_device_byte_transfer			0	0	--
V2	rx_timeout	spi_device_rx_timeout			0	0	--
V2	bit_transfer_on_spi	spi_device_bit_transfer			0	0	--
V2	extreme_fifo_setting	spi_device_extreme_fifo_size			0	0	--
V2	perf	spi_device_perf			0	0	--
V2	csb_read	spi_device_csb_read	0.920s	39.950us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	180.683us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	25.288us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	17.400s	2.012ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	17.400s	2.012ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	33.850s	26.075ms	50	50	100.00
		spi_device_tpm_sts_read	1.290s	210.691us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.197m	57.676ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	53.950s	35.280ms	50	50	100.00
		spi_device_flash_all	6.065m	304.514ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	44.880s	15.347ms	50	50	100.00
		spi_device_flash_all	6.065m	304.514ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	44.880s	15.347ms	50	50	100.00
		spi_device_flash_all	6.065m	304.514ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.065m	304.514ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	14.440s	4.160ms	50	50	100.00
		spi_device_flash_all	6.065m	304.514ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	14.440s	4.160ms	50	50	100.00
		spi_device_flash_all	6.065m	304.514ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	14.440s	4.160ms	50	50	100.00
		spi_device_flash_all	6.065m	304.514ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	14.440s	4.160ms	50	50	100.00
		spi_device_flash_all	6.065m	304.514ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	49.060s	19.000ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	41.290s	47.105ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	41.290s	47.105ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	41.290s	47.105ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	49.140s	11.053ms	46	50	92.00
		spi_device_read_buffer_direct	7.310s	1.764ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	41.290s	47.105ms	50	50	100.00
		spi_device_flash_all	6.065m	304.514ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.065m	304.514ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.065m	304.514ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	12.290s	3.265ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	12.290s	3.265ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.348m	411.749ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	14.530m	252.096ms	48	50	96.00
V2	stress_all	spi_device_stress_all	20.817m	872.137ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.770s	23.288us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.790s	59.450us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.560s	1.490ms	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.560s	1.490ms	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.220s	123.987us	5	5	100.00
		spi_device_csr_rw	3.040s	140.896us	20	20	100.00
		spi_device_csr_aliasing	16.780s	2.525ms	5	5	100.00
		spi_device_same_csr_outstanding	5.080s	900.641us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.220s	123.987us	5	5	100.00
		spi_device_csr_rw	3.040s	140.896us	20	20	100.00
		spi_device_csr_aliasing	16.780s	2.525ms	5	5	100.00
		spi_device_same_csr_outstanding	5.080s	900.641us	20	20	100.00
V2		TOTAL			1024	1030	99.42
V2S	tl_intg_err	spi_device_sec_cm	1.210s	206.349us	5	5	100.00
		spi_device_tl_intg_err	23.070s	2.344ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.070s	2.344ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1114	1120	99.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	7	7	87.50
V2	36	23	21	58.33
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	98.38	94.43	98.61	89.36	97.08	95.82	98.22

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 2 failures:

Test spi_device_flash_mode has 2 failures.

39.spi_device_flash_mode.57285520692720723636832696611816442026042236342157365450253362164969841595909
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/39.spi_device_flash_mode/latest/run.log

  UVM_ERROR @ 332433454 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_ERROR @ 339473851 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 861008688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.spi_device_flash_mode.81593817245444685321301259695413769349876205242282693866024280042024712017250
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/40.spi_device_flash_mode/latest/run.log

  UVM_ERROR @ 172921387 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 603775123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (spi_device_scoreboard.sv:891) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 6.spi_device_flash_mode.72333839361331137341899405991055035969465155037780038225731771930624342663008
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/6.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 56181088420 ps: (spi_device_scoreboard.sv:891) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 56181088420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

17.spi_device_flash_and_tpm_min_idle.55635050517228407235057116902213616265246368944496896499920231976062242842868
Line 263, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 2851635309 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 2859176562 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 9/18
  UVM_INFO @ 2991178247 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 10/18
  UVM_INFO @ 3341220729 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 11/18
  UVM_INFO @ 3516271521 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 12/18

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare CmdFifoNotEmpty mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

24.spi_device_flash_and_tpm_min_idle.71468826370573231451706912810046614650766872631901857137092664372204238206405
Line 254, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 1826395954 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare CmdFifoNotEmpty mismatch, act (0x0) != exp 1
  UVM_INFO @ 2589443725 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 4/6
  UVM_INFO @ 3019706022 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 2/19
  UVM_INFO @ 3129489712 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 5/6
  UVM_INFO @ 4109454600 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 3/19

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_mode has 1 failures.

47.spi_device_flash_mode.29857114479197918570243487331002357659568757372997095642314704999893956418052
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/47.spi_device_flash_mode/latest/run.log

  UVM_ERROR @ 585753312 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare ReadbufWatermark mismatch, act (0x0) != exp 1
  UVM_ERROR @ 587086656 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare ReadbufWatermark mismatch, act (0x0) != exp 1
  UVM_ERROR @ 589142228 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare ReadbufWatermark mismatch, act (0x0) != exp 1
  UVM_ERROR @ 591864472 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare ReadbufWatermark mismatch, act (0x0) != exp 1
  UVM_ERROR @ 603086784 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare ReadbufWatermark mismatch, act (0x0) != exp 1