SPI_DEVICE Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: `0cdf265eaa`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_smoke			0	0	--
V1	csr_hw_reset	spi_device_csr_hw_reset	1.470s	206.299us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.940s	356.638us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.240s	560.022us	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.610s	3.922ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.940s	53.258us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.940s	356.638us	20	20	100.00
		spi_device_csr_aliasing	23.610s	3.922ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.730s	11.429us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.370s	208.623us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	base_random_seq	spi_device_txrx			0	0	--
V2	fifo_full	spi_device_fifo_full			0	0	--
V2	fifo_underflow_overflow	spi_device_fifo_underflow_overflow			0	0	--
V2	dummy_sck_and_dummy_csb	spi_device_dummy_item_extra_dly			0	0	--
V2	extra_delay_on_spi	spi_device_dummy_item_extra_dly			0	0	--
V2	tx_async_fifo_reset	spi_device_tx_async_fifo_reset			0	0	--
V2	rx_async_fifo_reset	spi_device_rx_async_fifo_reset			0	0	--
V2	interrupts	spi_device_intr			0	0	--
V2	abort	spi_device_abort			0	0	--
V2	byte_transfer_on_spi	spi_device_byte_transfer			0	0	--
V2	rx_timeout	spi_device_rx_timeout			0	0	--
V2	bit_transfer_on_spi	spi_device_bit_transfer			0	0	--
V2	extreme_fifo_setting	spi_device_extreme_fifo_size			0	0	--
V2	perf	spi_device_perf			0	0	--
V2	csb_read	spi_device_csb_read	0.980s	36.869us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.180s	60.845us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	18.033us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	8.140s	500.867us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	8.140s	500.867us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	35.550s	59.548ms	50	50	100.00
		spi_device_tpm_sts_read	1.120s	121.831us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.230m	27.804ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	47.790s	77.746ms	50	50	100.00
		spi_device_flash_all	7.827m	351.903ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	42.250s	58.702ms	50	50	100.00
		spi_device_flash_all	7.827m	351.903ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	42.250s	58.702ms	50	50	100.00
		spi_device_flash_all	7.827m	351.903ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	7.827m	351.903ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	13.660s	3.527ms	50	50	100.00
		spi_device_flash_all	7.827m	351.903ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	13.660s	3.527ms	50	50	100.00
		spi_device_flash_all	7.827m	351.903ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	13.660s	3.527ms	50	50	100.00
		spi_device_flash_all	7.827m	351.903ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	13.660s	3.527ms	50	50	100.00
		spi_device_flash_all	7.827m	351.903ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	42.540s	148.018ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	48.610s	15.427ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	48.610s	15.427ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	48.610s	15.427ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	54.120s	21.164ms	46	50	92.00
		spi_device_read_buffer_direct	7.990s	7.379ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	48.610s	15.427ms	50	50	100.00
		spi_device_flash_all	7.827m	351.903ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	7.827m	351.903ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	7.827m	351.903ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	8.900s	4.895ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	8.900s	4.895ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.504m	149.463ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.328m	91.176ms	49	50	98.00
V2	stress_all	spi_device_stress_all	27.557m	260.800ms	49	50	98.00
V2	alert_test	spi_device_alert_test	0.810s	92.699us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	18.783us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.650s	174.018us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.650s	174.018us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.470s	206.299us	5	5	100.00
		spi_device_csr_rw	2.940s	356.638us	20	20	100.00
		spi_device_csr_aliasing	23.610s	3.922ms	5	5	100.00
		spi_device_same_csr_outstanding	4.840s	205.862us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.470s	206.299us	5	5	100.00
		spi_device_csr_rw	2.940s	356.638us	20	20	100.00
		spi_device_csr_aliasing	23.610s	3.922ms	5	5	100.00
		spi_device_same_csr_outstanding	4.840s	205.862us	20	20	100.00
V2		TOTAL			1023	1030	99.32
V2S	tl_intg_err	spi_device_sec_cm	1.180s	168.887us	5	5	100.00
		spi_device_tl_intg_err	25.570s	4.702ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	25.570s	4.702ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1113	1120	99.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	7	7	87.50
V2	36	23	19	52.78
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	98.38	94.45	98.61	89.36	97.08	95.82	98.22

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 2 failures:
- Test spi_device_flash_mode has 2 failures.
  - 1.spi_device_flash_mode.102084322491419390690939727088136525455544868980767434030398030868275197180206
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 512245010 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 642530287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.spi_device_flash_mode.14016014707358060693618291491708040155350084995354840810465845323546676240852
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/3.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 902892639 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 1481030911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 2 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

26.spi_device_flash_and_tpm_min_idle.33353318574943548905221640864922008453752194272668083739681165201574974731945
Line 273, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 43644001500 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 43723724360 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 11/14
  UVM_INFO @ 44159616736 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 12/14
  UVM_INFO @ 44704648874 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 13/14
  UVM_INFO @ 45242736512 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 14/14

Test spi_device_stress_all has 1 failures.

47.spi_device_stress_all.114336089151800784123430553466871503946734487659934788809759355465076236010333
Line 276, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/47.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 26607406942 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1
  UVM_INFO @ 29212448942 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 4/17
  UVM_INFO @ 29493576942 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 4/16
  UVM_INFO @ 31173808942 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 5/17
  UVM_INFO @ 32326156942 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 5/16

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 2 failures:
- Test spi_device_flash_mode has 2 failures.
  - 29.spi_device_flash_mode.99778841603274008763928326048674631389630728840654003315496954638848396712516
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/29.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 520179144 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 748007204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.spi_device_flash_mode.34981590922759705996278662776383521394609113232459885854649948794465711636322
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/33.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 197911900 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 1794757968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [spi_device_flash_all_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:

Test spi_device_flash_all has 1 failures.

36.spi_device_flash_all.60679154445878759076158758125890112688329839875226710382598730626721831860192
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/36.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 612228903 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 647056985 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/11
  UVM_INFO @ 1077495489 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/11
  UVM_INFO @ 1333818099 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/11
  UVM_INFO @ 1649405889 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 6/11