SPI_DEVICE Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: `c30684b3ca`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	7.627m	913.969ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.150s	19.013us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.700s	1.791ms	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.660s	1.885ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	8.360s	2.070ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.990s	173.419us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.700s	1.791ms	20	20	100.00
		spi_device_csr_aliasing	8.360s	2.070ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	35.854us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.160s	69.106us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.900s	67.745us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	35.224us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.840s	32.219us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	13.820s	878.810us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	13.820s	878.810us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	36.350s	83.005ms	50	50	100.00
		spi_device_tpm_sts_read	1.130s	669.041us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.165m	13.472ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	44.960s	18.102ms	50	50	100.00
		spi_device_flash_all	5.307m	64.424ms	49	50	98.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	27.740s	51.081ms	50	50	100.00
		spi_device_flash_all	5.307m	64.424ms	49	50	98.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	27.740s	51.081ms	50	50	100.00
		spi_device_flash_all	5.307m	64.424ms	49	50	98.00
V2	cmd_info_slots	spi_device_flash_all	5.307m	64.424ms	49	50	98.00
V2	cmd_read_status	spi_device_intercept	15.010s	23.117ms	50	50	100.00
		spi_device_flash_all	5.307m	64.424ms	49	50	98.00
V2	cmd_read_jedec	spi_device_intercept	15.010s	23.117ms	50	50	100.00
		spi_device_flash_all	5.307m	64.424ms	49	50	98.00
V2	cmd_read_sfdp	spi_device_intercept	15.010s	23.117ms	50	50	100.00
		spi_device_flash_all	5.307m	64.424ms	49	50	98.00
V2	cmd_fast_read	spi_device_intercept	15.010s	23.117ms	50	50	100.00
		spi_device_flash_all	5.307m	64.424ms	49	50	98.00
V2	cmd_read_pipeline	spi_device_intercept	15.010s	23.117ms	50	50	100.00
		spi_device_flash_all	5.307m	64.424ms	49	50	98.00
V2	flash_cmd_upload	spi_device_upload	45.430s	46.451ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	58.560s	79.114ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	58.560s	79.114ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	58.560s	79.114ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	47.830s	17.291ms	49	50	98.00
		spi_device_read_buffer_direct	7.370s	6.315ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	58.560s	79.114ms	50	50	100.00
		spi_device_flash_all	5.307m	64.424ms	49	50	98.00
V2	quad_spi	spi_device_flash_all	5.307m	64.424ms	49	50	98.00
V2	dual_spi	spi_device_flash_all	5.307m	64.424ms	49	50	98.00
V2	4b_3b_feature	spi_device_cfg_cmd	12.750s	3.966ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	12.750s	3.966ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	7.627m	913.969ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.000m	1.500s	49	50	98.00
V2	stress_all	spi_device_stress_all	13.690m	135.708ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.780s	13.427us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	16.169us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.330s	176.230us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.330s	176.230us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.150s	19.013us	5	5	100.00
		spi_device_csr_rw	2.700s	1.791ms	20	20	100.00
		spi_device_csr_aliasing	8.360s	2.070ms	5	5	100.00
		spi_device_same_csr_outstanding	4.130s	228.537us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.150s	19.013us	5	5	100.00
		spi_device_csr_rw	2.700s	1.791ms	20	20	100.00
		spi_device_csr_aliasing	8.360s	2.070ms	5	5	100.00
		spi_device_same_csr_outstanding	4.130s	228.537us	20	20	100.00
V2		TOTAL			977	980	99.69
V2S	tl_intg_err	spi_device_sec_cm	1.380s	922.770us	5	5	100.00
		spi_device_tl_intg_err	21.340s	3.804ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.340s	3.804ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1117	1120	99.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	19	86.36
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	98.39	94.44	98.61	89.36	97.10	95.82	98.22

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_and_tpm_min_idle has 1 failures.
  - 14.spi_device_flash_and_tpm_min_idle.113830242791430499079013040933939855796154791865957398700947626818038855067872
    Line 274, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:1024) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_flash_all has 1 failures.

22.spi_device_flash_all.90901735100636632403499694348315759466331009039999509776680236066423529146083
Line 256, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/22.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 8405486270 ps: (spi_device_scoreboard.sv:1024) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x92377c) != exp '{'{other_status:'h20a3ea, wel:'h0, busy:'h0}, '{other_status:'h37f210, wel:'h0, busy:'h0}}
  UVM_INFO @ 8468366270 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 7/8
  UVM_INFO @ 9724526270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (spi_device_scoreboard.sv:891) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 31.spi_device_flash_mode.37488104572084315033633518515673121260891618590649774318472134530276472745868
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/31.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 25293460677 ps: (spi_device_scoreboard.sv:891) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 25293460677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```