SPI_DEVICE/1R1W Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.853m	288.753ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.520s	68.494us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.580s	83.404us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.870s	2.706ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.720s	4.299ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.200s	929.630us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.580s	83.404us	20	20	100.00
		spi_device_csr_aliasing	24.720s	4.299ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.680s	39.877us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.350s	54.775us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.850s	25.852us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.750s	1.785us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.820s	22.291us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	11.210s	1.177ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.210s	1.177ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.790s	34.502ms	50	50	100.00
		spi_device_tpm_sts_read	1.260s	176.001us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.294m	42.362ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	39.920s	30.093ms	50	50	100.00
		spi_device_flash_all	5.208m	124.283ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	43.140s	36.477ms	50	50	100.00
		spi_device_flash_all	5.208m	124.283ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	43.140s	36.477ms	50	50	100.00
		spi_device_flash_all	5.208m	124.283ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.208m	124.283ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	21.610s	32.082ms	50	50	100.00
		spi_device_flash_all	5.208m	124.283ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	21.610s	32.082ms	50	50	100.00
		spi_device_flash_all	5.208m	124.283ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	21.610s	32.082ms	50	50	100.00
		spi_device_flash_all	5.208m	124.283ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	21.610s	32.082ms	50	50	100.00
		spi_device_flash_all	5.208m	124.283ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	21.610s	32.082ms	50	50	100.00
		spi_device_flash_all	5.208m	124.283ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	47.090s	68.294ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.094m	86.319ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.094m	86.319ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.094m	86.319ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.171m	23.436ms	49	50	98.00
		spi_device_read_buffer_direct	8.470s	2.225ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.094m	86.319ms	50	50	100.00
		spi_device_flash_all	5.208m	124.283ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.208m	124.283ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.208m	124.283ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	13.700s	4.040ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	13.700s	4.040ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.853m	288.753ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.196m	466.594ms	50	50	100.00
V2	stress_all	spi_device_stress_all	19.672m	385.912ms	49	50	98.00
V2	alert_test	spi_device_alert_test	0.860s	30.904us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	16.549us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.440s	296.083us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.440s	296.083us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.520s	68.494us	5	5	100.00
		spi_device_csr_rw	2.580s	83.404us	20	20	100.00
		spi_device_csr_aliasing	24.720s	4.299ms	5	5	100.00
		spi_device_same_csr_outstanding	4.380s	812.902us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.520s	68.494us	5	5	100.00
		spi_device_csr_rw	2.580s	83.404us	20	20	100.00
		spi_device_csr_aliasing	24.720s	4.299ms	5	5	100.00
		spi_device_same_csr_outstanding	4.380s	812.902us	20	20	100.00
V2		TOTAL			958	980	97.76
V2S	tl_intg_err	spi_device_sec_cm	1.350s	169.167us	5	5	100.00
		spi_device_tl_intg_err	22.910s	1.022ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.910s	1.022ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1098	1120	98.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	19	86.36
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	98.38	94.44	98.61	89.36	97.08	95.82	98.22

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.27693416266492954664680868808488956354022177578095723704380533042201172302191
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    935390 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[65])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    935390 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    935390 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[961])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.107583737828876829876623125174797088196274325188885730736563103135424471440682
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   5018314 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[23])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   5018314 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   5018314 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[919])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 0.spi_device_flash_mode.72185461053896591661888945389049237337502716285400978379399308891736416211805
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 692550548 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 946296409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:1024) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_stress_all has 1 failures.

38.spi_device_stress_all.66516670609143518425100378014230601346814610149987312222989669381105848596125
Line 257, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/38.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 535766935 ps: (spi_device_scoreboard.sv:1024) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x808838) != exp '{'{other_status:'h20220e, wel:'h0, busy:'h1}}
  UVM_INFO @ 614008754 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/8
  UVM_INFO @ 639001261 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/17
  UVM_INFO @ 1170409426 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/8
  UVM_INFO @ 1249891983 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/17