SPI_DEVICE/2P Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: `36c168c253`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.221m	469.619ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.560s	76.958us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.780s	375.649us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	34.760s	1.047ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.610s	672.672us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.070s	263.843us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.780s	375.649us	20	20	100.00
		spi_device_csr_aliasing	16.610s	672.672us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	14.154us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.280s	579.922us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	0.870s	16.662us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.130s	24.694us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	16.787us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	14.340s	381.346us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	14.340s	381.346us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	29.960s	9.663ms	50	50	100.00
		spi_device_tpm_sts_read	1.230s	165.966us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.238m	12.102ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	41.990s	14.490ms	50	50	100.00
		spi_device_flash_all	6.718m	199.294ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	46.560s	37.192ms	50	50	100.00
		spi_device_flash_all	6.718m	199.294ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	46.560s	37.192ms	50	50	100.00
		spi_device_flash_all	6.718m	199.294ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.718m	199.294ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	18.340s	21.840ms	50	50	100.00
		spi_device_flash_all	6.718m	199.294ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	18.340s	21.840ms	50	50	100.00
		spi_device_flash_all	6.718m	199.294ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	18.340s	21.840ms	50	50	100.00
		spi_device_flash_all	6.718m	199.294ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	18.340s	21.840ms	50	50	100.00
		spi_device_flash_all	6.718m	199.294ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	18.340s	21.840ms	50	50	100.00
		spi_device_flash_all	6.718m	199.294ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	52.920s	17.162ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.509m	72.619ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.509m	72.619ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.509m	72.619ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.072m	14.274ms	45	50	90.00
		spi_device_read_buffer_direct	7.560s	8.039ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.509m	72.619ms	50	50	100.00
		spi_device_flash_all	6.718m	199.294ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.718m	199.294ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.718m	199.294ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	14.140s	7.317ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	14.140s	7.317ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.221m	469.619ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.455m	1.228s	49	50	98.00
V2	stress_all	spi_device_stress_all	11.252m	205.370ms	49	50	98.00
V2	alert_test	spi_device_alert_test	0.800s	39.265us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.880s	12.744us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.480s	706.563us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.480s	706.563us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.560s	76.958us	5	5	100.00
		spi_device_csr_rw	2.780s	375.649us	20	20	100.00
		spi_device_csr_aliasing	16.610s	672.672us	5	5	100.00
		spi_device_same_csr_outstanding	4.690s	1.487ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.560s	76.958us	5	5	100.00
		spi_device_csr_rw	2.780s	375.649us	20	20	100.00
		spi_device_csr_aliasing	16.610s	672.672us	5	5	100.00
		spi_device_same_csr_outstanding	4.690s	1.487ms	20	20	100.00
V2		TOTAL			973	980	99.29
V2S	tl_intg_err	spi_device_sec_cm	1.240s	173.406us	5	5	100.00
		spi_device_tl_intg_err	23.490s	1.641ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.490s	1.641ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1113	1120	99.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	22	22	19	86.36
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	98.38	94.44	98.61	89.36	97.08	95.82	98.22

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 2 failures:
- Test spi_device_flash_mode has 2 failures.
  - 0.spi_device_flash_mode.44543553966022419338122817620863347654259964999798885448138259447842947128352
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 552405556 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 3519512586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.spi_device_flash_mode.33755047724889785249566992649362238924129839451331241700751904132484765572427
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/22.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 226330626 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_INFO @ 413057678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (spi_device_scoreboard.sv:891) [scoreboard] timeout occurred! has 2 failures:
- Test spi_device_flash_mode has 2 failures.
  - 5.spi_device_flash_mode.93929513247819412349886295114939233766079283745897369904668833509075491757642
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/5.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 37576861631 ps: (spi_device_scoreboard.sv:891) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 37576861631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.spi_device_flash_mode.17397904820682741660632562761951416284946531166770816251360453859834577970498
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/16.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 12378919075 ps: (spi_device_scoreboard.sv:891) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 12378919075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:1024) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 2 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

23.spi_device_flash_and_tpm_min_idle.76160231160176163488201734952169441137640175242925292036499503665461609153976
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 5457340064 ps: (spi_device_scoreboard.sv:1024) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2aef9e) != exp '{'{other_status:'habbe7, wel:'h0, busy:'h0}}
  UVM_INFO @ 5748351064 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 5/7
  UVM_INFO @ 6743577064 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 6/7
  UVM_INFO @ 8878340064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_stress_all has 1 failures.

41.spi_device_stress_all.759382454684452238182271063974876911567733095256219846700875339876558805662
Line 263, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/41.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 2177212581 ps: (spi_device_scoreboard.sv:1024) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xae504c) != exp '{'{other_status:'h2b9413, wel:'h0, busy:'h1}}
  UVM_INFO @ 4131706581 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 1/13
  UVM_INFO @ 6257612581 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/4
  UVM_INFO @ 6448120581 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/13
  UVM_ERROR @ 10042292581 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare PayloadOverflow mismatch, act (0x0) != exp 1

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 40.spi_device_flash_mode.23901812519684086151353444127082195410221568855438303835567650272189114133857
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/40.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 708460995 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 1252014878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```