SPI_DEVICE/1R1W Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: `8d1fda3660`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.805m	140.740ms	49	50	98.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.480s	50.941us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.570s	303.473us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.910s	2.346ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.520s	629.014us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.380s	55.525us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.570s	303.473us	20	20	100.00
		spi_device_csr_aliasing	21.520s	629.014us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.690s	13.459us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.200s	27.138us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	csb_read	spi_device_csb_read	0.890s	58.271us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.180s	121.844us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	26.690us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	13.250s	1.418ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	13.250s	1.418ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	33.930s	13.384ms	50	50	100.00
		spi_device_tpm_sts_read	1.200s	573.201us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.195m	13.997ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.066m	22.691ms	50	50	100.00
		spi_device_flash_all	9.159m	238.287ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	40.680s	14.676ms	50	50	100.00
		spi_device_flash_all	9.159m	238.287ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	40.680s	14.676ms	50	50	100.00
		spi_device_flash_all	9.159m	238.287ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.159m	238.287ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	14.950s	27.431ms	50	50	100.00
		spi_device_flash_all	9.159m	238.287ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	14.950s	27.431ms	50	50	100.00
		spi_device_flash_all	9.159m	238.287ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	14.950s	27.431ms	50	50	100.00
		spi_device_flash_all	9.159m	238.287ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	14.950s	27.431ms	50	50	100.00
		spi_device_flash_all	9.159m	238.287ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	14.950s	27.431ms	50	50	100.00
		spi_device_flash_all	9.159m	238.287ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	42.970s	12.589ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.035m	20.094ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.035m	20.094ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.035m	20.094ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.730m	33.366ms	48	50	96.00
		spi_device_read_buffer_direct	7.570s	3.172ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.035m	20.094ms	50	50	100.00
		spi_device_flash_all	9.159m	238.287ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.159m	238.287ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.159m	238.287ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	20.880s	108.924ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	20.880s	108.924ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.805m	140.740ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.700m	510.541ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.442m	189.638ms	48	50	96.00
V2	alert_test	spi_device_alert_test	0.810s	24.277us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.810s	87.937us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.850s	482.903us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.850s	482.903us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.480s	50.941us	5	5	100.00
		spi_device_csr_rw	2.570s	303.473us	20	20	100.00
		spi_device_csr_aliasing	21.520s	629.014us	5	5	100.00
		spi_device_same_csr_outstanding	3.810s	229.503us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.480s	50.941us	5	5	100.00
		spi_device_csr_rw	2.570s	303.473us	20	20	100.00
		spi_device_csr_aliasing	21.520s	629.014us	5	5	100.00
		spi_device_same_csr_outstanding	3.810s	229.503us	20	20	100.00
V2		TOTAL			976	980	99.59
V2S	tl_intg_err	spi_device_sec_cm	1.210s	113.005us	5	5	100.00
		spi_device_tl_intg_err	24.140s	3.429ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.140s	3.429ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1115	1120	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	20	90.91
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	98.38	94.45	98.61	89.36	97.08	95.82	98.22

Failure Buckets

UVM_ERROR (spi_device_pass_base_vseq.sv:643) [flash_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 2 failures:

Test spi_device_flash_and_tpm has 1 failures.

25.spi_device_flash_and_tpm.87156516701955910117800359165850400176424903389532353576395354717372222062525
Line 287, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/25.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 19652066673 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 20242075540 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 18/19
  UVM_INFO @ 21163480070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_stress_all has 1 failures.

31.spi_device_stress_all.50102463755719678050898978410669422825325016888151590988830136556779028736680
Line 299, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/31.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 15782226798 ps: (spi_device_pass_base_vseq.sv:643) [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
  UVM_INFO @ 16138476298 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 6/19
  UVM_INFO @ 17120751798 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 7/19
  UVM_INFO @ 17820300298 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 8/19
  UVM_INFO @ 18090743298 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 9/19

UVM_ERROR (spi_device_scoreboard.sv:1054) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 0.spi_device_flash_mode.5897138203529903998015483072285979062129540560957781790651754461633811957286
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/0.spi_device_flash_mode/latest/run.log
```
  UVM_ERROR @ 595902085 ps: (spi_device_scoreboard.sv:1054) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_INFO @ 661255286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:477) [scoreboard] Check failed flash_status_q.size <= * (* [*] vs * [*]) has 1 failures:

Test spi_device_stress_all has 1 failures.

10.spi_device_stress_all.42316549849160052243633341260447437446277790801323249330674889898149149250432
Line 294, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/10.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 50359223021 ps: (spi_device_scoreboard.sv:477) [uvm_test_top.env.scoreboard] Check failed flash_status_q.size <= 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 50590477021 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 11/16
  UVM_INFO @ 52042318021 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 12/16
  UVM_INFO @ 57186490021 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 13/16
  UVM_INFO @ 58876748021 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 14/16

UVM_FATAL (spi_device_scoreboard.sv:891) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 35.spi_device_flash_mode.67431781270334727185406239036450177695486331290236383084518005348656909413383
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device-sim-vcs/35.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 23377636238 ps: (spi_device_scoreboard.sv:891) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 23377636238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```